DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-10 without traverse in the reply filed on 05/28/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Nakano [US 2012/0049202].
► With respect to claim 1, Nakano (fig 4A-4Q, 6A-6O,text [0001]-[0243]) discloses a method of manufacturing a semiconductor device comprising:
providing a substrate, wherein the substrate is SiC base, and the substrate sequentially comprises, from bottom to top, an N-type heavy doping base layer (11, text [0133]), an N-type light doping layer (16, text [0135]), a P-well region (17, text [0136]), and a N-type heavy doping layer (45, text [0162]);
etching the substrate using a patterned mask (46, text [0163]) to form at least one gate trench and a channel region defined by the at least one gate trench, wherein the channel region is covered by the patterned mask;
performing an ion implantation process to the at least one gate trench to form a shielding implant layer (52, text [0186]) at a bottom surface of the at least one gate trench;
performing an oxidation process to the at least one gate trench to form a gate oxide layer (24, text [0188]) , wherein an oxidation rate at the bottom surface of the at least one gate trench is faster than an oxidation rate at a sidewall of the at least one gate trench; and
forming at least one gate electrode (29, text [0174]) in the at least one gate trench.
► With respect to claim 3, Nakano (fig 4A-4Q, 6A-6O ,text [0001]-[0243]) discloses further comprising removing the patterned mask (46, text [0168]-[0170]) after the performing the ion implantation process to the at least one gate trench.
► With respect to claim 4, Nakano (fig 4A-4Q, 6A-6O, ,text [0001]-[0243]) discloses further comprising performing an annealing process (text [0171]) after removing the patterned mask.
► With respect to claim 8, Nakano (fig 4A-4Q, 6A-6O, ,text [0001]-[0243]) inherently discloses wherein performing the ion implantation process to the at least one gate trench is performed vertical to the bottom surface of the at least one gate trench since there is no impurity outside the corner of the bottom trench.
► With respect to claim 10, Nakano (fig 4G, 6G, ,text [0001]-[0243]) discloses wherein etching the substrate using the patterned mask stops at the N-type light doping layer (16, text [0136]).
Claims 1, 2 and 6 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hiyoshi et al [US 2016/0163853].
► With respect to claim 1, Hiyoshi et al (fig 8A-8C, 10A-10C, text [0001]-[0138]) discloses a method of manufacturing a semiconductor device comprising:
providing a substrate, wherein the substrate is SiC base, and the substrate sequentially comprises, from bottom to top, an N-type heavy doping base layer (80, text [0067]), an N-type light doping layer (81, text [0067]), a P-well region (82, text [0068]), and a N-type heavy doping layer (83, text [0069]);
etching the substrate using a patterned mask (text [0104]-[0105]) to form at least one gate trench and a channel region defined by the at least one gate trench, wherein the channel region is covered by the patterned mask;
performing an ion implantation process to the at least one gate trench to form a shielding implant layer (81a, text [0110]) at a bottom surface of the at least one gate trench;
performing an oxidation process to the at least one gate trench to form a gate oxide layer (91, text [0112]) , wherein an oxidation rate at the bottom surface of the at least one gate trench is faster than an oxidation rate at a sidewall of the at least one gate trench; and
forming at least one gate electrode (92, text [0115]) in the at least one gate trench.
► With respect to claim 2, Hiyoshi et al discloses wherein ions utilized in the ion implantation process (81a, text [0110]) comprises P, As, or Ar.
► With respect to claim 6, Hiyoshi et al (fig 8A-8C, 10A-10C) discloses wherein etching the substrate to form at least one gate trench is performed such that the sidewall of the at least one gate trench has an inclined angle (fig. 8B, text [0104]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano [US 2012/0049202] in view of Adachi et al [2019/0206987]
► With respect to claim 5, Nakano disclose wherein the annealing process ([0171]) is performed at a temperature of about 1700 Celsius degrees but does not mention wherein the annealing process is performed in an inert gas environment for about 30 minutes. However, it is well known in the art to use the inert gas environment for about 30 minutes. See Adachi et al [text [0092] teaches annealing process is performed in an inert gas environment for about 30 minutes. Therefore, it would have been obvious to one skill in the art, in view of Adachi et al, to use inert gas to annealing the implant layer as being claimed in order to activate the implant layer. Moreover, selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co., Inc. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). The time range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi et al [US 2016/0163853].
Hiyoshi et al do not mention , wherein the inclined angle is in a range from 75 degrees to 105 degrees. However, the inclined angle range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it appears that these changes produce no functional differences and therefore would have been obvious. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi et al [US 2016/0163853] in view of TAKETANI et al [US 2012/0261714] IDS.
Hiyoshi et al fail to disclose wherein performing the ion implantation process to the at least one gate trench is performed inclined towards the channel region. However, TAKETANI et al (fig. 5) disclose performing the ion implantation process to the at least one gate trench (3, text [0056]) is performed inclined towards the channel region (4a, text [0056]). Therefore, it would have been obvious to one skill in the art to performing the ion implantation process as taught by TAKETANI et al into the method of Hiyoshi et al in order to retrict the channel layer from extending in the depth direction.
Conclusion
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812
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