DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(US20130248933A1) and Kinoshita(US20180012960A1).
Regarding Claim 1,
Ikeda teaches in FIG 2A, FIG 2B, FIG 5 and FIG 8A semiconductor device, comprising:
a substrate (FIG 5; 10; ¶[0027]);
a first semiconductor layer (FIG 5; 11; ¶[0027]) arranged above the substrate (FIG 5; 10; ¶[0027]);
a second semiconductor layer (FIG 5; 12; ¶[0020]) arranged on the first semiconductor layer (FIG 5; 11; ¶[0027]) to generate a two-dimensional electronic gas (FIG 2A and FIG 2B; 100 e and 200 e; ¶[0021] ¶[0024]);
a source electrode (FIG 2A; 40; ¶[0022]) and a drain electrode (FIG 2A; 50; ¶[0022]) arranged on the second semiconductor layer (FIG 5; 12; ¶[0020]);
a third semiconductor layer (FIG 2A; 13; ¶[0027]) arranged on the second semiconductor layer (FIG 5; 12; ¶[0020]) between the source electrode (FIG 2A; 40; ¶[0022]) and the drain electrode (FIG 2A; 50; ¶[0022]);
a gate electrode (FIG 2A; 30; ¶[0022]) arranged on the third semiconductor layer (FIG 2A; 13; ¶[0027]); and
a guard ring (FIG 2B; 70; ¶[0024]) arranged on the second semiconductor layer (FIG 5; 12; ¶[0020]), wherein
the second semiconductor layer (FIG 5; 12; ¶[0020]) defines a boundary between an element region (FIG 8A with annotations; 100; element region; ¶[0020]) in which a field-effect transistor (FIG 2A; 100; ¶[0020]; HEMT) is formed and an element separation region (FIG 8A with annotations; element separation region) surrounding the element region (FIG 8A; 100; ¶[0020]),
the field-effect transistor (FIG 2A; 100; ¶[0020]; HEMT) is formed of the first semiconductor layer (FIG 5; 11; ¶[0027]), the second semiconductor layer (FIG 5; 12; ¶[0020]), the third semiconductor layer (FIG 2A; 13; ¶[0027]), the gate electrode (FIG 2A; 30; ¶[0022]), the source electrode (FIG 2A; 40; ¶[0022]), and the drain electrode (FIG 2A; 50; ¶[0022]), and
the guard ring (FIG 2B; 70; ¶[0024]) is arranged in a peripheral part of the element region and includes a
a first electrode (FIG 2B; 60; ¶[0024]) arranged on the fourth semiconductor layer and electrically connected to the source electrode or the two-dimensional electronic gas (¶[0024]; shielding layer 60 is in ohmic contact with the 2DEG).
Ikeda does not teach
a second semiconductor layer arranged on the first semiconductor layer to generate a two-dimensional electronic gas in the first semiconductor layer in a vicinity of an interface between the second semiconductor layer and the first semiconductor layer;
a source electrode and a drain electrode arranged on the second semiconductor layer and electrically connected to the two-dimensional electronic gas;
a third semiconductor layer arranged on the second semiconductor layer between the source electrode and the drain electrode and including an acceptor impurity;
the guard ring is arranged in a peripheral part of the element region and includes a fourth semiconductor layer arranged on the second semiconductor layer and including an acceptor impurity, and
Kinoshita teaches in FIG 2, FIG 8, ¶[0118] and ¶[0063]
a second semiconductor layer (FIG 2; 103; ¶[0063]) arranged on the first semiconductor layer (FIG 2; 102; ¶[0063]) to generate a two-dimensional electronic gas (2DEG; ¶[0063]) in the first semiconductor layer (FIG 2; 102; ¶[0063]) in a vicinity of an interface between the second semiconductor layer (FIG 2; 103; ¶[0063]) and the first semiconductor layer (FIG 2; 102; ¶[0063]);
a source electrode (FIG 8; 107; ¶[0065]) and a drain electrode (FIG 8; 108; ¶[0065]) arranged on the second semiconductor layer (FIG 2; 103; ¶[0063]) and electrically connected to the two-dimensional electronic gas (2DEG; ¶[0063]; ¶[0118]; distance between the 2DEG layer and source electrode 107 and the distance between the 2DEG layer and drain electrode 108 can be reduced, making it possible to reduce contact resistance; The distance between the 2DEG layer and source and drain layer effects the electron movement (resistance));
a third semiconductor layer (FIG 2; 105; ¶[0065]; p-type) arranged on the second semiconductor layer (FIG 2; 103; ¶[0063]) between the source electrode (FIG 2; 107; ¶[0065]) and the drain electrode (FIG 2; 108; ¶[0065]) and including an acceptor impurity;
a fourth semiconductor layer (FIG 8; 310; ¶[0130]; p-type nitride) arranged on the second semiconductor layer (FIG 8; 203; ¶[0086]) and including an acceptor impurity, and
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure and the art of Kinoshita, a semiconductor device with a 2DEG layer at the first and second interface, a third semiconductor layer with an acceptor impurity and a fourth semiconductor layer with an acceptor impurity. This combination produces a semiconductor device with a stacked structure with a 2DEG layer at the first and second interface, a third semiconductor layer with an acceptor impurity and a fourth semiconductor layer with an acceptor impurity. The fourth semiconductor layer acts as a hole injector into an active semiconductor layer Kinoshita(¶[0130]).
PNG
media_image1.png
684
944
media_image1.png
Greyscale
Regarding Claim 2, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 2B and ¶[0063] wherein the first electrode (FIG 2B; 60; ¶[0024]) is electrically connected to the two-dimensional electronic gas (2DEG; ¶[0063]) located adjacent to an inner edge of the guard ring in plan view (FIG 2B; 60; ¶[0024]; The shielding layer 60 and the 2DEG are electrically connected).
Regarding Claim 3, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 2B wherein the element separation region (FIG 2B with annotation; element separation region) includes the substrate and the first semiconductor layer (FIG 2B; 11; ¶[0027]), and the second semiconductor layer (FIG 2B; 12; ¶[0020]) is removed from the element separation region (FIG 2B with annotation; element separation region; portions of 12 are inside element separation region).
PNG
media_image2.png
828
1280
media_image2.png
Greyscale
Regarding Claim 4, Ikeda and Kinoshita teach the semiconductor device according to claim 3.
Ikeda teaches in FIG 2B wherein the first semiconductor layer (FIG 2B; 11; ¶[0027]) and the substrate (FIG 2B; 10; ¶[0027]) are cut at the element separation region (FIG 2B with annotations; 10 and 11; inside element separation region).
Regarding Claim 5, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 2B wherein the first semiconductor layer includes GaN (FIG 2B; 11; ¶[0027]), and
Ikeda does not teach the second semiconductor layer includes AlGaN.
Kinoshita teaches in FIG 2 the second semiconductor layer includes AlGaN (FIG 2; 103; ¶[0064])
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure with a first semiconductor layer including GaN and the art of Kinoshita, a semiconductor device with a second semiconductor layer including AlGaN. This combination produces a semiconductor device with a stacked structure with a first semiconductor layer including GaN and a second semiconductor layer including AlGaN. The first semiconductor layer including GaN and the second semiconductor layer containing AlGaN so the 2DEG layer can be formed (Kinoshita(¶[0064])).
Regarding Claim 6, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 2A wherein the drain electrode (FIG 2A; 50; ¶[0022]) is surrounded by the third semiconductor layer (FIG 2A; 13; ¶[0020]) in plan view.
Regarding Claim 7, Ikeda teaches the semiconductor device according to claim 1.
Ikeda teaches in FIG 2A wherein the source electrode (FIG 2A; 40; ¶[0022]), the gate electrode (FIG 2A; 30; ¶[0022]), and the drain electrode (FIG 2A; 50; ¶[0022]) are repeatedly arranged in a first direction so that the source electrode (FIG 2A; 40; ¶[0022]), the gate electrode (FIG 2A; 30; ¶[0022]), and the drain electrode (FIG 2A; 50; ¶[0022]) are separated and adjacent to each other in the first direction (FIG 2A; first direction) in plan view and the gate electrode (FIG 2A; 30; ¶[0022]) is located between the source electrode (FIG 2A; 40; ¶[0022]) and the drain electrode (FIG 2A; 50; ¶[0022]).
PNG
image3.png
100
100
image3.png
Greyscale
Regarding Claim 8, Ikeda and Kinoshita teaches the semiconductor device according to claim 7.
Ikeda teaches in FIG 8A wherein the guard ring (FIG 8A with annotation; 70; ¶[0024]) is located adjacent to the source electrode (FIG 8A with annotations; 40(S); ¶[0022]) in the first direction.
PNG
image4.png
100
100
image4.png
Greyscale
Regarding claim 9, Ikeda and Kinoshita teaches the semiconductor device according to claim 8.
Ikeda teaches in FIG 2A, FIG 2B the two-dimensional electronic gas (FIG 2A and FIG 2B; 100 e and 200 e; ¶[0021] ¶[0024]) between the source electrode (FIG 2A; 40; ¶[0022]) and the guard ring (FIG 2B; 70; ¶[0024]) located adjacent to the source electrode (FIG 2A; 40; ¶[0022])
Ikeda does not teach wherein the two-dimensional electronic gas extending in the first semiconductor layer
the two-dimensional electronic gas has a source potential.
Kinoshita teaches in FIG 2 and FIG 12, wherein the two-dimensional electronic gas (2DEG; ¶[0157]) extending in the first semiconductor layer (FIG 2; 103; ¶[0063])
the two-dimensional electronic gas has a source potential (FIG 12; 107; ¶[0157]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure and the art of Kinoshita, a semiconductor device with a 2DEG layer at the first and second interface with a source electrode has a source potential. This combination produces a semiconductor device with a stacked structure with a 2DEG layer with a source electrode has a source potential. The source potential influences the flow of electrons in the 2DEG layer ¶[0157] effecting the performance of the semiconductor device.
Regarding Claim 10, Ikeda and Kinoshita teaches the semiconductor device according to claim 1.
Ikeda and Kinoshota do not teach wherein the fourth semiconductor layer has a width that is greater than a width of the third semiconductor layer in the first direction.
However, the ordinary artisan would have recognized the width of the fourth semiconductor layer and the third semiconductor layer to be a result effective variable affecting the mobility of the electrons moving throughout the transistor. Thus, it would have been obvious to limit the width of the fourth semiconductor layer and third semiconductor layer within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding Claim 12, Ikeda and Kinoshita teach the semiconductor device according to claim 1
Ikeda does not teach wherein the field-effect transistor is of a normally-off type.
Kinoshita teaches in ¶[0066] wherein the field-effect transistor is of a normally-off type (¶[0066]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure and the art of Kinoshita, a semiconductor device with a 2DEG layer at the first and second interface and the transistor is normally -off type. This combination produces a semiconductor device with a stacked structure with a 2DEG layer and the transistor is normally off-type. This device can be used high-power switching semiconductor devices that are normally off ¶[0177].
Regarding Claim 13, Ikeda and Kinoshita teach the semiconductor device according to claim 1. Ikeda teaches in FIG 5 wherein the first electrode (FIG 5; 60; ¶[0028]) and the
Ikeda does not teach gate electrode are formed from a same material.
Kinoshita teaches in FIG 8, gate electrode (FIG 8; 106; ¶[0076]) are formed from a same material.
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure with a first electrode comprising Ti and the art of Kinoshita, a semiconductor device with a gate electrode comprising Ti. This combination produces a semiconductor device with a stacked structure both, a first electrode and a gate electrode being formed of Ti. The first electrode and gat electrode being formed of the same material (Kinoshita¶[0076]) allows for the same manufacture process to produce both layers.
Regarding Claim 14, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 2A wherein the first electrode (FIG 2A; 60; ¶[0024]), the source electrode (FIG 2A; 50; ¶[0028]), and the drain electrode (FIG 2A; 50; ¶[0028]) are formed from a same material.
Regarding Claim 15, Ikeda and Kinoshita teach the semiconductor device according to claim 14.
Ikeda teaches in FIG 5, wherein the first electrode includes a first electrode part (FIG 5; 60b; ¶[0049]), and
a second electrode part (FIG 5; 60a; ¶[0049]) arranged on the second semiconductor layer (FIG 5; 12; ¶[0020]) and formed integrally with the first electrode part.
Ikeda does not teach arranged on the fourth semiconductor layer
Kinoshita teaches in FIG 8, arranged on the fourth semiconductor layer (FIG 8; 310; ¶[0130])
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda, a semiconductor device with a stacked structure with a first electrode with a first part and second part and the art of Kinoshita, a semiconductor device with a fourth semiconductor layer. This combination produces a semiconductor device with a stacked structure with a first electrode with a first part and second part and a fourth semiconductor layer. The fourth semiconductor layer acts as a hole injector into an active semiconductor layer Kinoshita(¶[0130]).
Regarding Claim 16, Ikeda and Kinoshita teach the semiconductor device according to claim 1.
Ikeda teaches in FIG 8A wherein the guard ring (FIG 8A; 60(70); ¶[0065]) is one of guard rings (FIG 8A; 61(71); ¶[0065]) arranged on the second semiconductor layer in the peripheral part of the element region.
Claims 11 rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(US20130248933A1) and Kinoshita(US20180012960A1) as applied to claims 1-10 and 12-16 above, and further in view of Marata(US20050001235).
Regarding Claim 11, Ikeda and Kimoshita teach the semiconductor device according to claim 1.
Ikeda and Kimoshita do not teach wherein the substrate is electrically conductive and is set to be equal in potential to the source electrode.
Murata teaches in FIG 1, wherein the substrate (FIG 1; 11; ¶[0058]) is electrically conductive and is set to be equal in potential to the source electrode (FIG 1; 16; ¶[0058]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Ikeda and Kinoshita, a semiconductor device with stacked layers, and the prior art of Murata, a semiconductor device with a conductive substrate set to be equal in potential to the source electrode. This combination produces a semiconductor device with stacked layers and a conductive substrate set to be equal in potential to the source electrode. This produces high frequency characteristics and high power characteristics of the transistor Murata (¶[0062]).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(US20130248933A1) and Kinoshita(US20180012960A1) as applied to claims 1-10 and 12-16 above, and further in view of Chen(US20190267456A1).
Regarding Claim 19, Ikeda and Kinoshita teach, the semiconductor device according to claim1.
Ikeda and Kinoshita do not further comprising: a source pad connected to the source electrode;
a drain pad connected to the drain electrode; and
a gate pad connected to the gate electrode, wherein at least a portion of the source pad, at least a portion of the drain pad, or at least a portion of the gate pad is present in an active region surrounded by the peripheral part of the element region in plan view.
Chen teaches in FIG 14B and FIG 2B further comprising: a source pad (FIG 14B; 17; ¶[0095]) connected to the source electrode (FIG 2B; 13; ¶[0095]);
a drain pad (FIG 14B; 18; ¶[0095]) connected to the drain electrode (FIG 14B; 4; ¶[0095]); and
a gate pad (FIG 14B; 11; ¶[0016]) connected to the gate electrode (FIG 14B; 10; ¶[0016]), wherein at least a portion of the source pad, at least a portion of the drain pad, or at least a portion of the gate pad is present in an active region (FIG 14B with annotations; active region) surrounded by the peripheral part of the element region (FIG 14B with annotations; Element region; taken to mean region where a transistor is formed) in plan view.
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda and Kinoshita, a semiconductor device with a stacked structure with and the art of Kinoshita, a semiconductor device a source, source pad, drain, drain pad, gate and gate pad and an active region surrounded by the element region. This combination produces a semiconductor device with a stacked structure with a source, source pad, drain, drain pad, gate and gate pad and an active region surrounded by the element region. The source pads and drain pad Chen(¶[0018]) are designed to control the flow of electrons through the transistor.
PNG
image5.png
100
100
image5.png
Greyscale
Regarding Claim 20, Ikeda and Kinoshita teach the semiconductor device according to claim 19.
Ikeda and Kinoshita do not teach wherein at least a portion of the source pad and at least a portion of the drain pad are present in the active region in plan view, the semiconductor device further comprising:
a source connection electrode formed from a material that differs from that of the source pad and connecting at least a portion of the source pad and the source electrode; and
a drain connection electrode formed from a material that differs from that of the drain pad and connecting at least a portion of the drain pad and the drain electrode.
Chen teaches in FIG 2 and FIG 3A wherein at least a portion of the source pad and at least a portion of the drain pad are present in the active region in plan view, the semiconductor device further comprising:
a source connection electrode (FIG 2; 3; ¶[0007]) formed from a material that differs from that of the source pad (FIG 2; 2; ¶[0007]) and connecting at least a portion of the source pad (FIG 2; 2; ¶[0007]) and the source electrode (FIG 3A; 13; ¶[0079]); and
a drain connection electrode (Fig 2; 5; ¶[0007]) formed from a material that differs from that of the drain pad (FIG 2; 4; ¶[0007]) and connecting at least a portion of the drain pad (FIG 2; 4; ¶[0007]) and the drain electrode (FIG 3A; 14; ¶[0079]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the art of Ikeda and Kinoshita, a semiconductor device with a stacked structure with and the art of Kinoshita, a semiconductor device with a source connection electrode and a drain connection electrode. This combination produces a semiconductor device with a stacked structure with a source connection electrode and a drain connection electrode. The source and drain connection electrodes Chen(¶[0017]) are used in high power transistors and controls the flow of electrons to support the performance of the semiconductor device.
Allowable Subject Matter
Claims 17 and 18 are objected to as being dependent upon a rejected base claim, but would
be allowable if rewritten in independent form including all of the limitations of the base claim and any
intervening claims.
Regarding Claim 17, the prior art of Arnold(US20210335781A1), either singularly or in combination, does not disclose or suggest the combination of limitations including further comprising: a second electrode arranged on the second semiconductor layer between the fourth semiconductor layer and the field-effect transistor in plan view and electrically connected to the two-dimensional electronic gas located immediately below the second electrode, wherein the second electrode is electrically connected to the first electrode.
Arnold discloses a second electrode arranged on the second semiconductor layer.
Regarding Claim 18, the prior art of Arnold(US20210335781A1), either singularly or in combination, does not disclose or suggest the combination of limitations including wherein the second electrode is located adjacent to the source electrode of the field-effect transistor, and the element separation region includes a first element separation region, the semiconductor device further comprising: a second element separation region formed between the second electrode and the source electrode.
Arnold discloses a second electrode is located adjacent to the source electrode of the field-effect transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Tsunami(US20210175337A1); This reference teaches a semiconductor device with stacked layers with a via-hole.
Takahashi(US10784368B2); This reference teaches a semiconductor device with an electron transit region through the middle down to the conductive substrate
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at 5712727925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.Q.R./ Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights