DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 12/23/2025. Claims 2-4 are have been cancelled. Claims 1 and 5-8 are pending in the Application, of which Claim 1 is independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
Continuity/ Priority Information
The present Application 18592718 filed 03/01/2024 claims foreign priority to JAPAN, Application 2023-037531, filed 03/10/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments, see Amendment/ Remarks filed 12/23/2025 with respect to the rejection of Claims 1 and 5-8 under 35 U.S.C. 102(a)(1) as being anticipated by Kawashima (Pub. No. US 20080057875), have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Kawashima does not teach or suggest changing the first squelch detection level or the second squelch detection level to increase or decrease in steps. Rather, in Kawashima, the output amplitude level of the differential signals is gradually changed and adjusted to exceed the first squelch detection level and not to exceed the second squelch detection level.
In response to Applicant arguments, the Examiner notes that increase or decrease the squelch setting value in steps, as claimed, is a design choice, which is functionally equivalent to the method in Kawashima of gradually adjusting the differential signals. Even though, the method in Kawashima differs of the claimed invention, both methods perform the same function of adjusting the squelch detection level in order to achieve an optimum result.
For example, Kawashima discloses in para. [0090] FIG. 7, a squelch detection receiver 206 switches the squelch detection levels according to a squelch detection level switching signal outputted by the controller 12. [0095] As an example of an arrangement of the squelch detection receiver 206 that is capable of setting plural squelch detection levels, there is a structure in which plural receivers having different squelch detection levels are arranged and one of the receivers is selected.
[0095] As an example of an arrangement of the squelch detection receiver 206 that is capable of setting plural squelch detection levels corresponding to “increase or decrease the squelch setting value in steps”, there is a structure in which plural receivers having different squelch detection levels are arranged and one of the receivers is selected.
[0069] Specifically, the squelch-signal-change detection counter 9, corresponding to “table configured to store the squelch setting value”, counts a change in the squelch signal outputted from the squelch detection receiver 6 according to the input of differential signals for test and outputs a count value of the count to the comparator 10.
Cleary, the squelch detection receiver 206 that switches the squelch detection levels as disclosed by Kawashima is functionally equivalent to " increase or decrease the squelch setting value in steps”, as Claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawashima (Pub. No. US 20080057875) Pub. Date: 2008-03-06.
Regarding independent Claim 1, Kawashima discloses an automatic adjustment circuit for amplitude of differential signal of a circuit in which electric signals used for transmission and reception are differential signals, comprising:
a signal reception circuit configured to receive a differential signal transmitted from another communication device via a communication cable, and convert the differential signal into binary data; a squelch detection circuit configured to compare an amplitude level of the differential signal with threshold voltages to detect a non-squelch state and a squelch state;
As shown in FIG. 1, [0043] The automatic adjustment circuit 100 for amplitude of differential signal includes a squelch detection receiver 6 that discriminates whether received differential signals are in an active state or a steady state (a squelch state) and a test loop-back circuit 7 that is capable of causing an output of the differential signal transceiver 1 and an input of the squelch detection receiver 6 to communicate with each other. The squelch state is a state in which a differential signal change indicating a meaningful data transfer state is not present on a differential signal line.
[0044] As shown in FIG. 4, the squelch detection receiver 6 has, for example, an output terminal 6a of the squelch detection receiver 6, an input terminal 6b of the squelch detection receiver 6 to which a differential signal RXP is inputted, an input terminal 6c of the squelch detection receiver 6 to which a differential signal RXN is inputted, a first differential amplifier 6d, to an input terminal 6b of which a non-inverting input terminal is connected and to an input terminal 6c of which an inverting input terminal is connected, a second differential amplifier 6e, to an input terminal 6b of which the inverting input terminal is connected and to an input terminal 6c of which the non-inverting input terminal is connected, and a NOR circuit 6f, to an input of which outputs of the first and second differential amplifiers 6d and 6e are connected and an output of which is connected to the output terminal 6a.
[0045] The squelch detection receiver 6 receives the differential signal RXP (TXP during a loop-back mode) and RXN (TXN during the loop-back mode), compares an amplitude level of the differential signals and a first squelch detection level set as a reference, and outputs a squelch signal according to a result of the comparison Thresholds of the first and second differential amplifiers 6d and 6e are set equal.
a start pattern detection circuit to enter a receivable state in response to a predetermined start pattern being detectable from the binary data based on the differential signal in a case where the squelch detection circuit detects the non-squelch state; [0056] As described above, the controller 12 can write the setting values in the amplitude setting register 2. The controller 12 controls the start and the end of transmission of a test pattern by the pattern generating circuit 4. The controller 12 can perform test pattern selection for the pattern generating circuit 4 or test pattern writing in the pattern generating circuit 4. [0064] Thereafter, the controller 12 causes the pattern generating circuit 4 to start transmission (output) of a test pattern for amplitude adjustment.
a register that stores a squelch setting value associated with the threshold voltages; a DC voltage selection circuit to select two DC voltages from among multiple DC voltages in accordance with the squelch setting value output from the register, and supply the two DC voltages as the threshold voltages to the squelch detection circuit;
[0090] FIG. 7 an arrangement of a main part of an automatic adjustment circuit 200 for amplitude of differential signal according to the second embodiment. As shown in FIG. 7, a squelch detection receiver 206, which functionally corresponds to the register with the DC voltage selection circuit, as claimed, switches the squelch detection levels according to a squelch detection level switching signal outputted by the controller 12. [0092] As shown in FIG. 7, a squelch detection receiver 206 switches the squelch detection levels according to a squelch detection level switching signal outputted by the controller 12. [0095] As an example of an arrangement of the squelch detection receiver 206 that is capable of setting plural squelch detection levels, there is a structure in which plural receivers having different squelch detection levels are arranged and one of the receivers is selected.
a squelch setting control circuit to, in response to the start pattern detection circuit detecting the receivable state, change the squelch setting value to increase or decrease the squelch setting value in steps and sequentially set the squelch setting value in the register.
[0099] The squelch detection receiver 206 switches the first squelch detection level and the second squelch detection level according to a squelch detection level switching signal outputted by the controller 12, compares the amplitude level of the differential signals and the second squelch detection level, and outputs a squelch signal according to a result of the comparison.
[0100] For example, as in the first embodiment, when the amplitude level of the differential signals is higher than the first squelch detection level (exceeds the first squelch detection level), the squelch detection receiver 206 outputs the squelch signal "Low". On the other hand, when the amplitude level of the differential signals is lower than the first squelch detection level (does not exceed the first squelch detection level), the squelch detection receiver 206 outputs the squelch signal "High".
a table configured to store the squelch setting value, wherein the squelch setting control circuit is further configured to sequentially store the squelch setting value in the table,
store, in response to the start pattern detection circuit detecting the receivable state, a success flag in the table in association with a squelch setting value used at time of the detecting of the receivable state,
read success flags associated with different squelch setting values from the table, count a number of success flags, and obtain a number of success steps, and
set the squelch setting value that enables successful reception to a center value of squelch setting values of the success steps or a value closer to a maximum squelch setting value by one step among middle squelch setting values of the success steps. [0072] The controller 12 changes the setting values in the amplitude setting register 2, causes the amplitude control circuit 3 to output a differential amplitude control signal, and slightly changes an output differential amplitude of the differential signal transceiver 1. The change may be in a direction for increasing the amplitude or in a direction for reducing the amplitude.
[0073] Specifically, the controller 12 causes, according to the setting values stored in the amplitude setting register 2, the amplitude control circuit 3 to change an output amplitude level of the differential signals for test outputted by the differential signal transceiver 1.
Regarding Claims 5-6, Kawashima discloses wherein in a case where the number of success steps is an odd number, the squelch setting control circuit sets the squelch setting value that enables successful reception to the center value of the squelch setting values of the success steps; and wherein in a case where the number of success steps is an even number, the squelch setting control circuit sets the squelch setting value that enables successful reception to the value closer to the maximum squelch setting value by one step among the middle squelch setting values of the success steps. [0058] The controller 12 performs control of a storage destination when a comparison result, corresponding to flags, of the comparator 10 is stored in the comparison result memory 11 according to the memory write control signal. The controller 12 performs readout of the comparison result stored in the comparison result memory 11.
[0059] An operation during a test for determining an output amplitude level of differential signals of the automatic adjustment circuit 100 for amplitude of differential signal having the structure described above will be explained.
[0071] The controller 12 controls, according to a memory write control signal, when and in which address of the comparison result memory 11 the difference value is written. Consequently, the comparison result memory 11 stores the difference value in association with the output amplitude level of the differential signals for test. Basically, the controller 12 performs the writing of the difference value in the comparison result memory 11 when the controller 12 judges that the transmission of the test pattern to the pattern generating circuit 4 is completed.
Regarding Claim 7, Kawashima discloses wherein the squelch setting control circuit sequentially sets, in the register, the squelch setting value that is changed to increase or decrease in steps, and in response to the start pattern detection circuit detecting a transition of the receivable state to a not-receivable state, switches the squelch setting value set in the register to a value that is smaller than the squelch setting value used at time of the detecting of the transition by one step or two steps.
[0056] As described above, the controller 12 can write the setting values in the amplitude setting register 2. The controller 12 controls the start and the end of transmission of a test pattern by the pattern generating circuit 4, corresponding to start pattern detection circuit. The controller 12 can perform test pattern selection for the pattern generating circuit 4 or test pattern writing in the pattern generating circuit 4.
Regarding Claim 8, Kawashima discloses an image forming apparatus and process comprising the communication device. FIG. 1 is a block diagram showing an arrangement of a main part of an automatic adjustment circuit 100 for amplitude of differential signal according to a first embodiment of the present invention.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Govindaraman (US 20040153696) FIG. 2 shows one example of data recovery module 114. [0043] When host 102 transmits signal 151 to peripheral 106(1), hub/repeater 104 receives signal 151 at upstream port 112. Input component 201 of data recovery module 114 then receives signal 151 from upstream port 112 over interface 120. At this point, respective inputs of squelch detector 218 and differential receiver 220 both receive signal 151. Squelch detector 218 thereby detects that upstream port 112 received signal 151, and sends signal 251 to port select logic 204 and multiplexer 206.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 28, 2026
Non-Final Rejection 20260127
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV