DETAILED ACTION
This Office Action is in response to Application filed on March 1, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II and Species B drawn to a HEMT device as recited in claim 1 and subspecies i drawn to the embodiment shown in Fig. 2, where the passivation region is an insulating material, claims 1-8, 18-20, and newly added claims 21-29, in the reply filed on June 3, 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because of the following reasons:
The structure of the claimed limitation “at least partially through the insulating structure” (claims 2, 19 and 29) is not shown in Fig. 2, because the first current conducting terminal and the control terminal appear to be adjacent to the insulating structure rather than through the insulating structure.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 19, and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation “at least partially through the insulating structure” recited in claims 2, 19, and 29 is indefinite because the preposition "through" would require the insulating structure on both sides of the conducting terminal, which Applicants did not show in the drawings. The first current conducting terminal, second current conducting terminal, and control terminal (recited in claims 2, 19, and 29) cannot extend partially through the insulating structure because this would prevent the proper functioning of the device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7, 18, and 21, as best understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (CHINA 2021105636827; Yang et al. (US 2022/0376100 A1) is used as a translation in current Office Action) hereinafter referred to as “Yang”.
Regarding claim 1, as best understood, Yang discloses a HEMT device (Fig. 10) comprising: a semiconductor body having a semiconductive heterostructure (element 101) ([0021]); a gate region (elements 108a and 108b) ([0022]) on the semiconductor body, the gate region (elements 108a and 108b) having a plurality of lateral sides; a plurality of sealing regions (element 126) of a first non-conductive material ([0023]), extending on and in contact with the plurality of lateral sides of the gate region (elements 108a and 108b); and a passivation layer (element 128) of a second non-conductive material ([0023]), the passivation layer (element 128) having surface portions extending on the semiconductor body, laterally and at a distance from the plurality of lateral sides of the gate region (elements 108a and 108b), the plurality of sealing regions (element 126) and the passivation layer (element 128) having different geometrical parameters; and a plurality of spacer regions (element 131) extending laterally and in contact with the plurality of sealing regions (element 126), because Applicants do not specifically claim what the spacer regions are formed of, and an air gap is a dielectric material with a dielectric constant of about 1, the passivation layer (element 128) having raised portions extending on the plurality of spacer regions (element 131), because the preposition “on” does not necessarily suggest “directly on”, laterally and at a distance from the plurality of sealing regions (element 126), because Applicants do not specifically claim what “a distance” refers to, whether “a distance” is a non-zero distance, and in addition, without Applicants’ specifically claiming what the “raised portions” of the passivation layer refer to, the “raised portions” can be arbitrarily selected to meet the claimed limitation even for a non-zero distance since again the preposition “on” does not necessarily suggest “directly on”.
Regarding claim 3, Yang discloses the HEMT device according to claim 1, wherein the sealing regions (element 126) are of an insulating material ([0023]).
Regarding claim 5, Yang discloses the HEMT device according to claim 1, wherein the passivation layer (element 128) is of an insulating material ([0023]).
Regarding claim 7, Yang discloses the HEMT device according to claim 1, wherein the passivation layer (element 128) have a greater thickness than the plurality of sealing regions (element 126).
Please refer to the explanations of the corresponding limitations above.
Regarding claim 18, as best understood, Yang discloses a HEMT device (Fig. 10) comprising: a semiconductor body having a semiconductive heterostructure (element 101); a gate region (elements 108a and 108b) on the semiconductor body, the gate region (elements 108a and 108b) having a plurality of lateral sides; a plurality of sealing regions (element 126) of a first non-conductive material ([0023]), extending on and in contact with the plurality of lateral sides of the gate region (elements 108a and 108b); and a passivation layer (element 128) of a second non-conductive material ([0023]), the passivation layer (element 128) having surface portions extending on the semiconductor body, laterally and at a distance from the plurality of lateral sides of the gate region (elements 108a and 108b), the plurality of sealing regions (element 126) and the passivation layer (element 128) being of different material ([0023]); and a plurality of spacer regions (element 131) extending laterally and in contact with the plurality of sealing regions (element 126), the passivation layer (element 128) having raised portions extending on the plurality of spacer regions (element 131), laterally and at a distance from the plurality of sealing regions (element 126).
Regarding claim 20, Yang discloses the HEMT device of claim 18 wherein the plurality of sealing regions (element 126) and the passivation layer (element 128) having different geometrical parameters.
Regarding claim 21, as best understood, Yang discloses a device, comprising: a semiconductor body having a first surface (element 106) opposite a second surface (element 104) along a first direction; a gate region (elements 108a and 108b) on the first surface of the semiconductor body, the gate region including a first region (element 108a) having a plurality of sidewalls extending along the first direction; a plurality of sealing regions (element 126) on each of the plurality of sidewalls of the gate region (elements 108a and 108b), respectively; a plurality of spacer regions (element 131) on each of the plurality of sealing regions (element 126), respectively; and a passivation layer (element 128) extending on the semiconductor body, and on each of the plurality of spacer regions (element 131), the passivation layer (element 128) being separated from the plurality of sealing regions (element 126) by the plurality of spacer regions (element 131).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 6, 19, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CHINA 202110563682.7; Yang et al. (US 2022/0376100 A1) is used as a translation in current Office Action) in view of Banerjee et al. (US 2020/0335617) and further in view of Chen et al. (US 2021/0175343).
Regarding claim 2, Yang discloses the HEMT device according to claim 1, further comprising: the first and second non-conductive materials being different materials ([0023]).
Yang does not disclose an insulating structure extending above the semiconductor body, laterally and on top of the gate region.
Banerjee discloses an insulating structure (Fig. 7, element 500) extending above the semiconductor body, laterally and on top of the gate region (Fig. 7, element 124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a semiconductor device such as a transistor device to comprise the insulating layer disclosed by Banerjee formed on top of the gate region disclosed by Chen, because it has been a common practice in semiconductor industry to form a plurality of dielectric layers on a semiconductor device to better protect the semiconductor device from the ambient and from the subsequent manufacturing processes; also, a plurality of dielectric layers would allow one of ordinary skill in the art to better control the overall dielectric constant of the plurality of dielectric layers such that cross-talk among the semiconductor device elements can be reduced, which would improve performance of the semiconductor device; in addition, a plurality of dielectric layers have been commonly formed for forming electrical contact structures for a semiconductor device by patterning the plurality of dielectric layers according to the design of the overall semiconductor device.
Yang in view of Banerjee does not disclose a first current conducting terminal extending on and in contact with the semiconductor body laterally to a first lateral side of the plurality of lateral sides of the gate region, at least partially through the insulating structure; a second current conducting terminal extending on and in contact with the semiconductor body laterally to a second side of the plurality of lateral sides of the gate region, at least partially through the insulating structure; and a control terminal extending on and in contact with the gate region, at least partially through the insulating structure.
Chen discloses a first current conducting terminal (Chen, Fig. 6, element 30) extending on and in contact with the semiconductor body laterally to a first lateral side of the plurality of lateral sides of the gate region (Chen, Fig. 6, element 18); a second current conducting terminal (Chen, Fig. 6, element 32) extending on and in contact with the semiconductor body laterally to a second side of the plurality of lateral sides of the gate region (Chen, Fig. 6, element 18); and a control terminal (Chen, Fig. 6, element 28) extending on and in contact with the gate region (Chen, Fig. 6, element 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the HEMT device disclosed by Yang in view of Banerjee can comprise the configuration of the current conducting terminals as disclosed by Chen, because it has been a common practice in semiconductor industry to employ dielectric material layers to form conducting terminals or vias/plugs to better align the conducting terminals or vias/plugs to the underlying device structure, which would improve the yield of the semiconductor devices, reducing the manufacturing cost.
Regarding claim 4, Yang in view of Banerjee and further in view of Chen discloses the HEMT device according to claim 1, wherein the plurality of sealing regions have a thickness between 2 and 10 nm.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to improve device performance by optimizing the claimed range of sealing region thickness such as reducing gate current leakage.
Regarding claim 6, Chen in view of Briere discloses the HEMT device according to claim 1, wherein the passivation layer have a thickness between 2 and 10 nm.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to improve device performance by optimizing the claimed range of passivation layer thickness such as reducing gate current leakage.
Regarding claim 19, Yang discloses the HEMT device of claim 18, as described previously.
Yang does not disclose an insulating structure extending above the semiconductor body, laterally and on top of the gate region.
Banerjee discloses an insulating structure (Fig. 7, element 500) extending above the semiconductor body, laterally and on top of the gate region (Fig. 7, element 124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a semiconductor device such as a transistor device to comprise the insulating layer disclosed by Banerjee formed on top of the gate region disclosed by Chen, because it has been a common practice in semiconductor industry to form a plurality of dielectric layers on a semiconductor device to better protect the semiconductor device from the ambient and from the subsequent manufacturing processes; also, a plurality of dielectric layers would allow one of ordinary skill in the art to better control the overall dielectric constant of the plurality of dielectric layers such that cross-talk among the semiconductor device elements can be reduced, which would improve performance of the semiconductor device; in addition, a plurality of dielectric layers have been commonly formed for forming electrical contact structures for a semiconductor device by patterning the plurality of dielectric layers according to the design of the overall semiconductor device.
Yang in view of Banerjee does not disclose a first current conducting terminal extending on and in contact with the semiconductor body laterally to a first lateral side of the plurality of lateral sides of the gate region, at least partially through the insulating structure; a second current conducting terminal extending on and in contact with the semiconductor body laterally to a second side of the plurality of lateral sides of the gate region, at least partially through the insulating structure; and a control terminal extending on and in contact with the gate region, at least partially through the insulating structure.
Chen discloses a first current conducting terminal (Chen, Fig. 6, element 30) extending on and in contact with the semiconductor body laterally to a first lateral side of the plurality of lateral sides of the gate region (Chen, Fig. 6, element 18); a second current conducting terminal (Chen, Fig. 6, element 32) extending on and in contact with the semiconductor body laterally to a second side of the plurality of lateral sides of the gate region (Chen, Fig. 6, element 18); and a control terminal (Chen, Fig. 6, element 28) extending on and in contact with the gate region (Chen, Fig. 6, element 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the HEMT device disclosed by Yang in view of Banerjee can comprise the configuration of the current conducting terminals as disclosed by Chen, because it has been a common practice in semiconductor industry to employ dielectric material layers to form conducting terminals or vias/plugs to better align the conducting terminals or vias/plugs to the underlying device structure, which would improve the yield of the semiconductor devices, reducing the manufacturing cost.
Regarding claim 29, Yang discloses the device of claim 21, as described previously.
Yang does not disclose an insulating structure extending on the semiconductor body and on the gate region.
Banerjee discloses an insulating structure (Fig. 7, element 500) extending above the semiconductor body, laterally and on top of the gate region (Fig. 7, element 124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a semiconductor device such as a transistor device to comprise the insulating layer disclosed by Banerjee formed on top of the gate region disclosed by Chen, because it has been a common practice in semiconductor industry to form a plurality of dielectric layers on a semiconductor device to better protect the semiconductor device from the ambient and from the subsequent manufacturing processes; also, a plurality of dielectric layers would allow one of ordinary skill in the art to better control the overall dielectric constant of the plurality of dielectric layers such that cross-talk among the semiconductor device elements can be reduced, which would improve performance of the semiconductor device; in addition, a plurality of dielectric layers have been commonly formed for forming electrical contact structures for a semiconductor device by patterning the plurality of dielectric layers according to the design of the overall semiconductor device.
Yang in view of Banerjee does not disclose a first current conducting terminal extending on and in contact with the semiconductor body and extending at least partially through the insulating structure along the first direction; and a control terminal extending on and in contact with the gate region, and extending at least partially through the insulating structure along the first direction.
Chen discloses a first current conducting terminal (Chen, Fig. 6, element 30) extending on and in contact with the semiconductor body; and a control terminal (Chen, Fig. 6, element 28) extending on and in contact with the gate region (Chen, Fig. 6, element 18).
Chen in view of Briere does not disclose an insulating structure extending on the semiconductor body and on the gate region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the HEMT device disclosed by Yang in view of Banerjee can comprise the configuration of the current conducting terminals as disclosed by Chen, because it has been a common practice in semiconductor industry to employ dielectric material layers to form conducting terminals or vias/plugs to better align the conducting terminals or vias/plugs to the underlying device structure, which would improve the yield of the semiconductor devices, reducing the manufacturing cost.
Claim(s) 8, and 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CHINA 2021105636827; Yang et al. (US 2022/0376100 A1) is used as a translation in current Office Action) in view of Chen et al. (US 2021/0175343).
Regarding claim 8, Yang discloses the HEMT device according to claim 6, as described previously.
Yang does not disclose the HEMT device according to claim 6, wherein the plurality of spacer regions is made of oxide.
Chen discloses the HEMT device according to claim 6, wherein the plurality of spacer regions (Chen, Fig. 6, element 22) is made of oxide ([0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention before the effective filing date of the claimed invention that the plurality of spacer regions can be made of oxide, because an air gap and an oxide material have been commonly and interchangeably employed as spacer materials in manufacturing transistors devices including HEMT devices, and the oxide space regions would allow one of ordinary skill in the art to control and optimize the dielectric constant of the space regions in a wider range of applications.
Regarding claim 22, Yang discloses the device of claim 21, as described previously.
Yang does not disclose the device of claim 21, wherein the gate region includes an interlayer region on the first region, the first region being a channel modulating region.
Chen discloses the device of claim 21, wherein the gate region (Chen, Fig. 6, element 18) includes an interlayer region (Chen, Fig. 6, element 20) on the first region (Chen, Fig. 6, element 18), the first region being a channel modulating region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention before the effective filing date of the claimed invention that a gate region of a transistor device including a HEMT device commonly includes a plurality of component layers to optimize the compatibility between gate material layers and the underlying device structure, while also controlling the bandgap structure and work function of the gate materials to improve performance of the transistor device.
Regarding claim 23, Yang in view of Chen discloses the device of claim 22, wherein the passivation layer (Chen, Fig. 6, element 26) extends onto the interlayer region (Chen, Fig. 6, element 20).
Regarding claim 24, Yang in view of Chen discloses the device of claim 23, wherein the passivation layer (Chen, Fig. 6, element 26) has a first opening on the interlayer region (Chen, Fig. 6, element 20), a gate metal (Chen, Fig. 6, element 28) being directly on the interlayer region (Chen, Fig. 6, element 20) through the first opening in the passivation layer (Chen, Fig. 6, element 26).
Regarding claim 25, Yang in view of Chen discloses, the device of claim 24, wherein the gate metal (Chen, Fig. 6, element 28) includes a first portion separated from the gate region (Chen, Fig. 6, element 18) along the first direction by the passivation layer (Chen, Fig. 6, element 26).
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CHINA 2021105636827; Yang et al. (US 2022/0376100 A1) is used as a translation in current Office Action) in view of Banerjee et al. (US 2020/0335617).
Regarding claim 26, Yang discloses the device of claim 25, as described previously.
Yang does not disclose the device of claim 25, further comprising a first insulating layer on the passivation layer, the first insulating layer being between the first portion of the gate metal and the gate region along the first direction.
Banerjee discloses a first insulating layer (Fig. 7, element 500) on the passivation layer (Fig. 7, element 444), the first insulating layer being between the first portion of the gate metal (Fig. 7, element 624) and the gate region (Fig. 7, element 124) along the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a semiconductor device such as a transistor device to comprise the insulating layer disclosed by Banerjee formed on top of the passivation layer disclosed by Chen, because it has been a common practice in semiconductor industry to form a plurality of dielectric layers on a semiconductor device to better protect the semiconductor device from the ambient and from the subsequent manufacturing processes; also, a plurality of dielectric layers would allow one of ordinary skill in the art to better control the overall dielectric constant of the plurality of dielectric layers such that cross-talk among the semiconductor device elements can be reduced, which would improve performance of the semiconductor device; in addition, a plurality of dielectric layers have been commonly formed for forming electrical contact structures for a semiconductor device by patterning the plurality of dielectric layers according to the design of the overall semiconductor device.
Regarding claim 27, Yang in view of Banerjee discloses the device of claim 26, further comprising a second insulating layer (Banerjee, Fig. 7, elements 600 and 700) on the first insulating layer (Banerjee, Fig. 7, element 500) and entirely covering the gate metal (Banerjee, Fig. 7, elements 624 and 6242).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (CHINA 2021105636827; Yang et al. (US 2022/0376100 A1) is used as a translation in current Office Action) in view of Coppens et al. (US 2022/0052163).
Regarding claim 28, Yang discloses the device of claim 27, as described previously.
Yang does not disclose the device of claim 27, further comprising a field plate between the first and second insulating layers.
Coppens discloses a field plate (Fig. 21, elements 2002 and 2004) between the first (Fig. 21, elements 2010 and 2012) and second insulating layers (Fig. 21, elements 2006 and 2008).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device disclosed by Chen et al. in view of Briere can further comprise a field plate between the first and second insulating layers as disclosed by Coppens et al., because a source, drain and/or gate field plate has been commonly implemented to better control distribution of the electric field in the channel region and thus the carrier mobility, which would improve performance of the semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
Prosecution Insights