Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/01/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-13, 17-18 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kan, US 20230135977, hereinafter Kan.
As per claim 9, Kan teaches A system comprising:
a plurality of sets of memory arrays (FIG.1, SRAM 108a... 108e);
a plurality of built-in self-test (BIST) engines; (FIG.1, [0024] one or more MBIST engines 106)
a register ([0030] the registers) to store one or more values ([0024] a test vector) indicating at least a partial order in which the plurality of BIST engines are to respectively test the plurality of sets of memory arrays; ([0034] the MBIST engine 106a may perform a first set of memory tests on a first region of its respective SRAM 108a using a first algorithm) and
a logic circuit (Fig.1 the programmable macro BIST controller 104) coupled to the register to cause the plurality of BIST engines to test the plurality of sets of memory arrays based on the one or more values stored in the register. ([0034] the MBIST engines 106 may perform memory tests on the SRAM 108 using the same or different algorithms according to the commands sent from the programmable macro BIST controller 104......)
As per claim 10, Kan teaches The system as applied above in claim 9, Kan further teaches wherein the one or more values stored in the register are determined based on tests in hardware or simulation. ([0062], [0069]-[0070])
As per claim 11, Kan teaches The system as applied above in claim 9, Kan further teaches wherein the one or more values stored in the register indicate an ordering of the plurality of BIST engines that balances power across a total period of testing. ([0030] the programmable macro BIST controller 104 may be configured to identify the SRAM power control switch 110 based on the instructions/data read (e.g., the test vector of the first type) from the registers.[0033])
As per claim 12, Kan teaches The system as applied above in claim 9, Kan further teaches wherein the logic circuit selects a first one of the BIST engines to run before other ones of the BIST engines based on the one or more values stored in the register, and wherein the other ones of the BIST engines run in a predetermined sequence following the running of the first one of the BIST engines. ([0042] The Macro_sel is a global MBIST sequence selection setting -indicating to each MBIST engine 106 of the sequence of memory test operations selected for execution.)
As per claim 13, Kan teaches The system as applied above in claim 12, Kan further teaches wherein the first one of the BIST engines sends a signal to a second one of the BIST engines upon completion of testing by the first one of the BIST engines to cause the second one of the BIST engines to begin testing. ([0042], [0034])
As per claim 16, Kan teaches The system as applied above in claim 9, Kan further teaches wherein the logic circuit causes a first subset of the BIST engines to run in parallel and a second subset of the BIST engines to run in a serial manner. ([0077] in other implementations, one or more operations, or portions thereof, are performed in a different order, or overlapping in time, in series or parallel, or are omitted, or one or more additional operations are added, or the method is changed in some combination of ways)
Claims 1-5, and 8 are method claim of claims 9-13, and 16 respectively, thus they are rejected under the same reason as claims 9-13, and 16 respectively.
Claims 17, 18 and 20 are apparatus claim of claims 9, 12, and 16 respectively, thus they are rejected under the same reason as claims 9, 12 and 16 respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 14-15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan, US 20230135977, hereinafter Kan, in view of Parulkar, US 6769081, hereinafter Parulkar.
As per claim 14, Kan teaches The system as applied above in claim 9, EXCEPT wherein the one or more values stored in the register indicate a complete order in which the plurality of BIST engines are to sequentially test the plurality of sets of memory arrays.
Parulkar teaches
wherein the one or more values stored in the register indicate a complete order in which the plurality of BIST engines are to sequentially test the plurality of sets of memory arrays. (15:45-50; FIG.12A, The BIST meta-controller 910 is essentially a state machine that sequences through the BIST tests for each of the sub-blocks of the memory under test.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kan to incorporate the teaching of the element as indicated above from Parulkar as indicated above, in order to efficiently and cost-effectively test IC devices (Kan, [0014]).
As per claim 15, Kan-Parulkar teaches The system as applied above in claim 14, Parulkar further teaches wherein the logic circuit includes a multiplexer coupled to the register to selectively output one of a plurality of possible orders of the BIST engines based on the one or more values stored in the register. (FIG.12B, 16:8-22 The working of the meta-controller is the same as the one in FIG. 12A, except that each BIST DONE signal from each memory sub-block is multiplexed with a "1" before sending it to the meta-controller. The input of the multiplexer is selected based on the value of the binary programmable element 1206.)
Claims 6-7 are method claim of claims 14-15 respectively, thus they are rejected under the same reason as claims 14-15 respectively.
Claims 19 is apparatus claim of claim 14, thus it is rejected under the same reason as claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chickanosky et al., US 20140129888, STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111