Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendment, filed 04/06/2026, has been received, entered into the record, respectfully and fully considered.
By this amendment, claims 1, 8, 9, 16, and 17 have been amended. Thus, claims 1 - 20 have been examined.
Any objection, claim interpretation and claim rejection not repeated below is withdrawn due to Applicant's amendments.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered and have been addressed as follows.
Applicant argued on page 8 of the remarks:
KAN does not disclose or suggest "wherein a first value of the one or more values indicates a first serial order of the plurality of BIST engines starting to test the plurality of sets of memory arrays, wherein a second value of the one or more values indicates a second serial order of the plurality of BIST engines starting to test the plurality of sets of memory arrays, and wherein the first serial order is different than the second serial order," as recited in claim 17, as amended.
This feature was not addressed by the Office Action. KAN is directed to " a programmable macro test for an integrated circuit" (paragraph 0001 of KAN). At paragraph 0030, KAN discloses that "the programmable macro BIST controller 104 may be configured to identify one or more MBIST engines 106 (e.g., MBIST engine 106 a, or MBIST engine 106 b, MBIST engine 106 c) of the plurality of MBIST engines 106 based on the instructions/data (e.g., the test vector of the first type) read from the registers." The Office Action alleges that the test vector correspond to the one or more values recited in the claims.
While KAN discloses that the registers store the instructions/data (or the test vector), KAN does not disclose or suggest that each instruction (or each test vector) indicates a different serial order of the MBIST engines beginning to sequentially test a plurality of sets of memory arrays. In other words, KAN does not disclose or suggest that a first instruction indicates a first serial order of the MBIST engines beginning to sequentially test a plurality of sets of memory arrays and a second instruction indicates a second serial order of the MBIST engines beginning to sequentially test a plurality of sets of memory arrays.
In response to Applicant’s Argument, Examiner would like to point out that
Parulkar teaches “wherein a first value of the one or more values indicates a first serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, wherein a second value of the one or more values indicates a second serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, and wherein the first serial order is different than the second serial order;”
(15:45-50; FIG.12A, The BIST meta-controller 910 is essentially a state machine that sequences through the BIST tests for each of the sub-blocks of the memory under test.)
“wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the first serial order when the first value is selected, and wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the second serial order when the second value is selected.”
(FIG.12B, 16:8-22 The working of the meta-controller is the same as the one in FIG. 12A, except that each BIST DONE signal from each memory sub-block is multiplexed with a "1" before sending it to the meta-controller. The input of the multiplexer is selected based on the value of the binary programmable element 1206.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan, US 20230135977, hereinafter Kan, in view of Parulkar, US 6769081, hereinafter Parulkar.
As per claim 9, Kan teaches A system comprising:
a plurality of sets of memory arrays (FIG.1, SRAM 108a... 108e);
a plurality of built-in self-test (BIST) engines; (FIG.1, [0024] one or more MBIST engines 106)
a register ([0030] the registers) to store one or more values ([0024] a test vector) indicating at least a partial order in which the plurality of BIST engines are to respectively test the plurality of sets of memory arrays; ([0034] the MBIST engine 106a may perform a first set of memory tests on a first region of its respective SRAM 108a using a first algorithm) and
a logic circuit (Fig.1 the programmable macro BIST controller 104) coupled to the register to cause the plurality of BIST engines to test the plurality of sets of memory arrays based on the one or more values stored in the register. ([0034] the MBIST engines 106 may perform memory tests on the SRAM 108 using the same or different algorithms according to the commands sent from the programmable macro BIST controller 104......)
EXCEPT
wherein each value of the one or more values indicates a different serial order of the plurality of BIST engines beginning to sequentially test the plurality of sets of memory arrays;
Parulkar teaches
wherein each value of the one or more values indicates a different serial order of the plurality of BIST engines beginning to sequentially test the plurality of sets of memory arrays;
(15:45-50; FIG.12A, The BIST meta-controller 910 is essentially a state machine that sequences through the BIST tests for each of the sub-blocks of the memory under test.)
(FIG.12B, 16:8-22 The working of the meta-controller is the same as the one in FIG. 12A, except that each BIST DONE signal from each memory sub-block is multiplexed with a "1" before sending it to the meta-controller. The input of the multiplexer is selected based on the value of the binary programmable element 1206.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kan to incorporate the teaching of the element as indicated above from Parulkar as indicated above, in order to efficiently and cost-effectively test IC devices (Kan, [0014]).
As per claim 17, Kan teaches An apparatus for reconfigurable testing of an integrated circuit, comprising:
a plurality of built-in self-test (BIST) engines; (FIG.1, [0024] one or more MBIST engines 106)
a register ([0030] the registers) to store one or more values ([0024] a test vector) indicating at least a partial order in which the plurality of BIST engines are to respectively test a plurality of sets of memory arrays, ([0034] the MBIST engine 106a may perform a first set of memory tests on a first region of its respective SRAM 108a using a first algorithm) and
a logic circuit (Fig.1 the programmable macro BIST controller 104) coupled to the register to cause the plurality of BIST engines to test the plurality of sets of memory arrays based on the one or more values stored in the register, (Fig.1 the programmable macro BIST controller 104)
EXCEPT
wherein a first value of the one or more values indicates a first serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, wherein a second value of the one or more values indicates a second serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, and wherein the first serial order is different than the second serial order;
wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the first serial order when the first value is selected, and wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the second serial order when the second value is selected.
Parulkar teaches
wherein a first value of the one or more values indicates a first serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, wherein a second value of the one or more values indicates a second serial order of the plurality of BIST engines beginning to test the plurality of sets of memory arrays, and wherein the first serial order is different than the second serial order;
wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the first serial order when the first value is selected, and wherein the plurality of BIST engines begin to test the plurality of sets of memory arrays in the second serial order when the second value is selected.
(15:45-50; FIG.12A, The BIST meta-controller 910 is essentially a state machine that sequences through the BIST tests for each of the sub-blocks of the memory under test.
FIG.12B, 16:8-22 The working of the meta-controller is the same as the one in FIG. 12A, except that each BIST DONE signal from each memory sub-block is multiplexed with a "1" before sending it to the meta-controller. The input of the multiplexer is selected based on the value of the binary programmable element 1206.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kan to incorporate the teaching of the element as indicated above from Parulkar as indicated above, in order to efficiently and cost-effectively test IC devices (Kan, [0014]).
As per claim 10, Kan-Parulkar teaches The system as applied above in claim 9, Kan further teaches wherein the one or more values stored in the register are determined based on tests in hardware or simulation. ([0062], [0069]-[0070])
As per claim 11, Kan-Parulkar teaches The system as applied above in claim 9, Kan further teaches wherein the one or more values stored in the register indicate an ordering of the plurality of BIST engines that balances power across a total period of testing. ([0030] the programmable macro BIST controller 104 may be configured to identify the SRAM power control switch 110 based on the instructions/data read (e.g., the test vector of the first type) from the registers.[0033])
As per claim 12, Kan-Parulkar teaches The system as applied above in claim 9, Kan further teaches wherein the logic circuit selects a first one of the BIST engines to run before other ones of the BIST engines based on the one or more values stored in the register, and wherein the other ones of the BIST engines run in a predetermined sequence following the first one of the BIST engines running. ([0042] The Macro_sel is a global MBIST sequence selection setting -indicating to each MBIST engine 106 of the sequence of memory test operations selected for execution.)
As per claim 13, Kan-Parulkar teaches The system as applied above in claim 12, Kan further teaches wherein the first one of the BIST engines sends a signal to a second one of the BIST engines upon completion of testing by the first one of the BIST engines to cause the second one of the BIST engines to begin testing. ([0042], [0034])
As per claim 14, Kan-Parulkar teaches The system as applied above in claim 9, Parulkar further teaches wherein the one or more values stored in the register indicate a complete order in which the plurality of BIST engines are to sequentially test the plurality of sets of memory arrays. (15:45-50; FIG.12A, The BIST meta-controller 910 is essentially a state machine that sequences through the BIST tests for each of the sub-blocks of the memory under test.)
As per claim 15, Kan-Parulkar teaches The system as applied above in claim 14, Parulkar further teaches wherein the logic circuit includes a multiplexer coupled to the register to selectively output one of a plurality of possible orders of the BIST engines based on the one or more values stored in the register. (FIG.12B, 16:8-22 The working of the meta-controller is the same as the one in FIG. 12A, except that each BIST DONE signal from each memory sub-block is multiplexed with a "1" before sending it to the meta-controller. The input of the multiplexer is selected based on the value of the binary programmable element 1206.)
As per claim 16, Kan-Parulkar teaches The system as applied above in claim 9, Kan further teaches wherein the logic circuit causes a first subset of the BIST engines to run in parallel and a second subset of the BIST engines to run in a serial manner. ([0077] in other implementations, one or more operations, or portions thereof, are performed in a different order, or overlapping in time, in series or parallel, or are omitted, or one or more additional operations are added, or the method is changed in some combination of ways)
Claims 1-8 are method claim of claims 9-16 respectively, thus they are rejected under the same reason as claims 9-16 respectively.
Claims 18 and 20 are apparatus claim of claims 12, and 16 respectively, thus they are rejected under the same reason as claims 9, 12 and 16 respectively.
Claims 19 is apparatus claim of claim 14, thus it is rejected under the same reason as claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chickanosky et al., US 20140129888, STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONG TANG whose telephone number is (469)295-9106. The examiner can normally be reached Monday - Friday 7:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RONG TANG/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111
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