DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 10 and 12-19 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lin et al. (US 2022/0216340, hereinafter Lin).
Regarding claim 1, Lin discloses for an integrated circuit device comprising that
a wimpy transistor stack (work piece 200, Fig. 17) on a substrate (substrate 202, Fig. 17), because Applicants do not specifically define what “wimpy” transistor is, what it looks like, and/or how it is distinct from conventional transistors, the vertical transistor stack in the workpiece 200 by Lin may correspond to the “wimpy” transistor in the claimed invention,
wherein the wimpy transistor stack (200, Fig. 17) comprises:
an upper transistor (upper transistor having an n-type electrode layers 266N, Fig. 17) comprising:
a plurality of upper channel regions (a plurality of channel layers 2080 at upper portion of 200 between 266N and above the gate dielectric layer 264, Fig. 17) stacked in a vertical direction (vertical direction in Fig. 17); and
an upper source/drain region (first top source/drain feature 248-1, Fig. 17) that contacts at least one of the plurality of upper channel regions (one of the two channel layers 2080 from the top of the workpiece 200, Fig. 17);
a lower transistor (lower transistor having a p-type electrode layers 266P, Fig. 17) that is between the substrate (202, Fig. 17) and the upper transistor (upper transistor having an n-type electrode layers 266N, Fig. 17) and comprises:
a plurality of lower channel regions (a plurality of 2080 at lower portion of 200 between 266P and below the gate dielectric layer 264, Fig. 17) stacked in the vertical direction (vertical direction in Fig. 17); and
a lower source/drain region (first bottom source/drain feature 228-1, Fig. 17) that contacts at least one of the plurality of lower channel regions (one of the four channel layers 2080 from the bottom of the workpiece 200, Fig. 17); and
a source/drain isolation layer (separation layer 242, Fig. 17, labeled in Figs. 8-10) separating the upper source/drain region (248-1, Fig. 17) from the lower source/drain region (228-1, Fig. 17),
wherein the source/drain isolation layer (242, Fig. 17, labeled in Figs. 8-10) contacts a lowermost one of the plurality of upper channel regions (channel layer 2080 directly above the gate dielectric layer 264, Fig. 17) and/or an uppermost one of the plurality of lower channel regions (channel layer 2080 directly below the gate dielectric layer 264, Fig. 17).
Regarding claim 2, Lin further discloses for the integrated circuit device of Claim 1 that the source/drain isolation layer (242, Fig. 17, labeled in Figs. 8-10) comprises an upper portion (upper portion of 242, Fig. 17) that extends into a space between the lowermost one of the plurality of upper channel regions (channel layer 2080 directly above the gate dielectric layer 264, Fig. 17) and the upper source/drain region (248-1, Fig. 17), because Applicants do not specifically claim what dimensions the claimed space have, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, the separation layer 242 by Lin vertically extends from the channel layer 2080 directly above 264 to the top source/drain feature 248-1 (see attached and annotated Fig. 17 of Lin below),
and/or the source/drain isolation layer (242, Fig. 17) comprises a lower portion (lower portion of 242, Fig. 17) that extends into a space between the uppermost one of the plurality of lower channel regions (2080 directly below 264, Fig. 17) and the lower source/drain region (228-1, Fig. 17).
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Regarding claim 3, Lin further discloses for the integrated circuit device of Claim 1 that the lowermost one of the plurality of upper channel regions (2080 directly above 264, Fig. 17) is electrically isolated from the upper source/drain region (248-1, Fig. 17), and/or the uppermost one of the plurality of lower channel regions (2080 directly below 264, Fig. 17) is electrically isolated from the lower source/drain region (228-1, Fig. 17)
Regarding claim 4, Lin further discloses for the integrated circuit device of Claim 1 that the source/drain isolation layer (242, Fig. 17, labeled in Figs. 8-10) contacts the lowermost one of the plurality of upper channel regions (2080 directly above 264, Fig. 17), and an upper surface of the lowermost one of the plurality of upper channel regions (top surface of 2080 directly above 264, Fig. 17) is spaced apart from the substrate (202, Fig. 17) by a first distance in the vertical direction (see attached and annotated Fig. 17 below), an upper surface of the source/drain isolation layer (top surface of 242, Fig. 17) is spaced apart from the substrate (202, Fig. 17) by a second distance in the vertical direction (see attached and annotated Fig. 17 below), and the second distance is equal to or greater than the first distance (see attached and annotated Fig. 17 below).
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Regarding claim 5, Lin further discloses for the integrated circuit device of Claim 1 that the source/drain isolation layer (242, Fig. 17, labeled in Figs. 8-10) contacts the uppermost one of the plurality of lower channel regions (2080 directly below 264, Fig. 17), and a lower surface of the uppermost one of the plurality of lower channel regions (bottom surface of 2080 directly below 264, Fig. 17) is spaced apart from the substrate (202, Fig. 17) by a third distance in the vertical direction (see attached and annotated Fig. 17 above), a lower surface of the source/drain isolation layer (bottom surface of 242, Fig. 17) is spaced apart from the substrate (202, Fig. 17) by a fourth distance in the vertical direction (see attached and annotated Fig. 17 above), and the third distance is equal to or greater than the fourth distance (see attached and annotated Fig. 17 above).
Regarding claim 6, Lin further discloses for the integrated circuit device of Claim 1 that the upper source/drain region (248-1, Fig. 17) is a first upper source/drain region (248-1, Fig. 17), the upper transistor (transistor having 266N, Fig. 17) further comprises a second upper source/drain region (second top source/drain feature 248-2, Fig. 17), and the plurality of upper channel regions (2080 at upper portion of 200 above 264, Fig. 17) are between the first upper source/drain region (248-1, Fig. 17) and the second upper source/drain region (248-2, Fig. 17), and the second upper source/drain region (248-2, Fig. 17) contacts the plurality of upper channel regions (2080 at upper portion of 200 above 264, Fig. 17), because the second top source/drain feature 248-2 by Lin is in contact with two channel layers 2080 from the top side of the workpiece 200 (Fig. 17).
Regarding claim 7, Lin further discloses for the integrated circuit device of Claim 6 that the lower source/drain region (228-1, Fig. 17) is a first lower source/drain region (228-1, Fig. 17), the lower transistor (transistor having 266P, Fig. 17) further comprises a second lower source/drain region (second bottom source/drain feature 228-2, Fig. 17), and the plurality of lower channel regions (2080 at lower portion of 200 below 264, Fig. 17) are between the first lower source/drain region (228-1, Fig. 17) and the second lower source/drain region (228-2, Fig. 17), and the second lower source/drain region contacts (228-2, Fig. 17) the plurality of lower channel regions (2080 at lower portion of 200 below 264, Fig. 17), because the second bottom source/drain feature 228-2 by Lin is in contact with three channel layers 2080 from the bottom side of the workpiece 200 (Fig. 17).
Regarding claim 10, Lin further discloses for the integrated circuit device of Claim 1 that the upper transistor (upper transistor of 200 having 266N, Fig. 17) is a first upper transistor (upper-left side of 200, Fig. 17), the plurality of upper channel regions (2080 at upper portion of 200 above 264, Fig. 17) are a plurality of first upper channel regions (2080 at upper-left side of 200, Fig. 17), the upper source/drain region (248-1, Fig. 17) is a first upper source/drain region (248-1, Fig. 17),
wherein the lower transistor (lower transistor of 200 having 266P, Fig. 17) is a first lower transistor (lower-left side of 200, Fig. 17), the plurality of lower channel regions (2080 at lower portion of 200 below 264, Fig. 17) are a plurality of first lower channel regions (2080 at lower-left side of 200, Fig. 17), and the lower source/drain region (228-1, Fig. 17) is a first lower source/drain region (228-1, Fig. 17), and
wherein the integrated circuit device further comprises a transistor stack (200, Fig. 17) comprising:
a second upper transistor (upper-middle side of 200, Fig. 17) comprising a plurality of second upper channel regions (2080 at upper-middle side of 200 above 264, Fig. 17) stacked in the vertical direction (stacked in the middle of Fig. 17), the plurality of second upper channel regions (two 2080 from the top of 200 at upper-middle side of 200 above 264, Fig. 17) contacting the first upper source/drain region (248-1, Fig. 17); and
a second lower transistor (lower-middle side of 200, Fig. 17) comprising a plurality of second lower channel regions (2080 at lower-middle side of 200 below 264, Fig. 17) stacked in the vertical direction (stacked in the middle of Fig. 17), the plurality of second lower channel regions (three 2080 from the bottom of 200 at lower-middle side of 200 below 264, Fig. 17) contacting the first lower source/drain region (228-1, Fig. 17).
Regarding claim 12, Lin further discloses for the integrated circuit device of Claim 10 that a number of the plurality of first upper channel regions (two 2080 at upper-left side of 200 above 264, Fig. 17) is equal to a number of the plurality of second upper channel regions (two 2080 at upper-middle side of 200 above 264, Fig. 17), and a number of the plurality of first lower channel regions (three 2080 at lower-left side of 200 below 264, Fig. 17) is equal to a number of the plurality of second lower channel regions (three 2080 at lower-middle side of 200 below 264, Fig. 17).
Regarding claim 13, Lin further discloses for the integrated circuit device of Claim 10 that a lower surface of a lowermost one of the plurality of first upper channel regions (bottom surface of 2080 at upper-left side of 200 directly above 264, Fig. 17) and a lower surface of a lowermost one of the plurality of second upper channel regions (bottom surface of 2080 at upper-middle side of 200 directly above 264, Fig. 17) are spaced apart from the substrate (202, Fig. 17) by an equal distance in the vertical direction, because the channel layer 2080 by Lin are symmetrically stacked in a vertical direction (Fig. 17), and an upper surface of an uppermost one of the plurality of first lower channel regions (top surface of 2080 at lower-left side of 200 directly below 264, Fig. 17) and an upper surface of an uppermost one of the plurality of second lower channel regions (top surface of an 2080 at lower-middle side of 200 directly below 264, Fig. 17) are spaced apart from the substrate (202, Fig. 17) by an equal distance in the vertical direction, because the channel layer 2080 by Lin are symmetrically stacked in a vertical direction (Fig. 17).
Regarding claim 14, Lin further discloses for an integrated circuit device, comprising that
a wimpy transistor stack (workpiece 200, Fig. 17) on a substrate (substrate 202, Fig. 17), because Applicants do not specifically define what “wimpy transistor” is, what it looks like, and/or how it is distinct from conventional transistors, the vertical transistor stack in the workpiece 200 by Lin may correspond to the “wimpy transistor” in the claimed invention,
wherein the wimpy transistor stack (200, Fig. 17) comprises:
an upper transistor (upper transistor of 200 having the n-type electrode 266N, Fig. 17) comprising:
a plurality of upper channel regions (three 2080 at upper portion of 200 above the gate dielectric layer 264, Fig. 17) stacked in a vertical direction (vertical direction in Fig. 17); and
an upper source/drain region (first top source/drain feature 248-1, Fig. 17) that contacts at least one of the plurality of upper channel regions (one of the three 2080 from the top of 200 above 264, Fig. 17); and
a lower transistor (lower transistor of 200 having the p-type electrode 266P, Fig. 17) that is between the substrate (202, Fig. 17) and the upper transistor (upper transistor having 266N, Fig. 17) and comprises:
a plurality of lower channel regions (four 2080 at lower portion of 200 below 264, Fig. 17) stacked in the vertical direction (vertical direction in Fig. 17); and
a lower source/drain region (first bottom source/drain feature 228-1, Fig. 17) that contacts at least one of the plurality of lower channel regions (one of four 2080 from the bottom of 200 below 264, Fig. 17),
wherein a lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) is electrically isolated from the upper source/drain region (248-1, Fig. 17), because the third 2080 from the top of the workpiece 200, which is positioned directly above the gate dielectric layer 264 is not in contact with the first top source/drain feature 248-1 (Fig. 17), and/or an uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 directly below 264, Fig. 17) is electrically isolated from the lower source/drain region (228-1, Fig. 17), because the fourth 2080 from the bottom of the workpiece 200, which is positioned directly below the gate dielectric layer 264 is not in contact with the first bottom source/drain feature 228-1 (Fig. 17).
Regarding claim 15, Lin further discloses for the integrated circuit device of Claim 14 that a source/drain isolation layer (separation layer 242, Fig. 17, labeled in Figs. 8-10) separating the upper source/drain region (248-1, Fig. 17) from the lower source/drain region (228-1, Fig. 17),
wherein the source/drain isolation layer (242, Fig, 17) separates the lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) from the upper source/drain region (248-1, Fig. 17), and/or the source/drain isolation layer (242, Fig. 17) separates the uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 directly below 264, Fig. 17) from the lower source/drain region (228-1, Fig. 17).
Regarding claim 16, Lin further discloses for the integrated circuit device of Claim 14 that a source/drain isolation layer (242, Fig. 17, labeled in Figs. 8-10) separating the upper source/drain region (248-1, Fig. 17) from the lower source/drain region (228-1, Fig. 17),
wherein the lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) is electrically isolated from the upper source/drain region (248-1, Fig. 17), and
the source/drain isolation layer (242, Fig. 17) comprises a portion that extends into a space between the lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) and the upper source/drain region (248-1, Fig. 17) and contacts the lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) (see the rejection of claim 2 and attached Fig. 17 of Lin).
Regarding claim 17, Lin further discloses for the integrated circuit device of Claim 14 that a source/drain isolation layer (242, Fig. 17) separating the upper source/drain region (248-1, Fig. 17) from the lower source/drain region (228-1, Fig. 17),
wherein the uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 directly below 264, Fig. 17) is electrically isolated from the lower source/drain region (228-1, Fig. 17), and
the source/drain isolation layer (242, Fig. 17) comprises a portion that extends into a space between the uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 directly below 264, Fig. 17) and the lower source/drain region (228-1, Fig. 17) and contacts the uppermost one of the plurality of lower channel regions (see the rejection of claim 2 and attached Fig. 17 of Lin).
Regarding claim 18, Lin further discloses for an integrated circuit device, comprising that
a wimpy transistor stack (workpiece 200, Fig. 17) on a substrate (substrate 202, Fig. 17), because Applicants do not specifically define what “wimpy transistor” is, what it looks like, and/or how it is distinct from conventional transistors, the vertical transistor stack in the workpiece 200 by Lin may correspond to the “wimpy transistor” in the claimed invention,
wherein the wimpy transistor stack (200, Fig. 17) comprises:
an upper transistor (upper portion of transistor having the n-type electrode 266N, Fig. 17) comprising:
a plurality of upper channel regions (2080 at upper portion of 200 above the gate dielectric layer 264, Fig. 17) stacked in a vertical direction (Fig. 17); and
an upper source/drain region (first top source/drain feature 248-1, Fig. 17) that contacts at least one of the plurality of upper channel regions (third 2080 from the top of 200 above 264, Fig. 17);
a lower transistor (lower portion of transistor having the p-type electrode 266P, Fig. 17) that is between the substrate (202, Fig. 17) and the upper transistor (upper portion of transistor having the n-type electrode 266N, Fig. 17) and comprises:
a plurality of lower channel regions (2080 at lower portion of 200 below 264, Fig. 17) stacked in the vertical direction (Fig. 17); and
a lower source/drain region (first bottom source/drain feature 228-1, Fig. 17) that contacts at least one of the plurality of lower channel regions (2080 at lower portion of 200 below 264, Fig. 17); and
a source/drain isolation layer (separation layer 242, Fig. 17, labeled in Figs. 8-10) separating the upper source/drain region (248-1, Fig. 17) from the lower source/drain region (228-1, Fig. 17),
wherein the source/drain isolation layer (242, Fig. 17) overlaps a lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 above 264, Fig. 17) and/or an uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 below 264, Fig. 17) in a horizontal direction (horizontal direction in Fig. 17).
Regarding claim 19, Lin further discloses for the integrated circuit device of Claim 18 that the source/drain isolation layer (242, Fig. 17) contacts the lowermost one of the plurality of upper channel regions (third 2080 from the top of 200 directly above 264, Fig. 17) and/or the uppermost one of the plurality of lower channel regions (fourth 2080 from the bottom of 200 directly below 264, Fig. 17).
Allowable Subject Matter
Claims 8-9, 11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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