Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-11 and 35, in the reply filed on 09/01/2026 is acknowledged. Claims 1-11 and 35 are examined below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “…the first metal film and the second metal film are provided between the semiconductor device and the first insulating layer…”. This is unclear, since “the semiconductor device” is the claimed overall device itself. For the purpose of examination, this limitation is interpretated as requiring the first metal film and second metal film to be provided between the signal line and the first insulating layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 10-11, 35 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Ryu (US 20220223732 A1).
Re: Independent Claim 1, Ryu discloses a semiconductor device comprising:
a first insulating layer (Ryu teaches, in Fig. 10, first insulating layer 112);
an oxide semiconductor formed in the first insulating layer, extending in a first direction, and having a first end and a second end (Ryu, Fig. 10 and ¶ [0039], oxide semiconductor channel layer 130 formed in first insulating layer 112; extending in Z-direction, and having first end adjacent first gate electrode 150A and another end adjacent second gate electrode 150B);
a first electrode including a first metal film that includes a first metal atom (Ryu, Fig. 10 and ¶ [0059], first landing pad 160A+165A includes tungsten (W), corresponding to the first metal film including the first metal atom W), and a first conductive film that is formed between the first metal film and the first end of the oxide semiconductor and includes metal oxide (Ryu, Fig. 10 and ¶ [0095], first contact pattern 165A is interposed between first end of oxide semiconductor channel layer 130 and first landing pad 160A; and 165A may include indium tin oxide (ITO) (¶ [0096]);
a second electrode in contact with the second end of the oxide semiconductor (conductive line 120 in contact with the lower portion of channel layer 130 (¶ [0030]));
at least a pair of gate electrodes that face each other via an insulating film (first and second gate electrodes 150A and 150B facing each other via insulating layer 114), and are interposed between the first end and the second end of the oxide semiconductor (150A and 150B are interposed between first end and second end of 130); and
a first structure that is separated from the first electrode in a second direction intersecting the first direction (Ryu teaches, in Fig. 10, second landing pad 160B separate from first electrode 160A+165A in X-direction intersecting the Z-direction), includes at least the first metal atom and does not include the metal oxide (Ryu teaches, in ¶ [0059], 160B may comprise Tungsten (W), and therefore the same first metal atom W of first landing pad 160A, and not including the metal oxide ITO of contact pattern 165A).
Re: Claim 2, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
further comprising: a second insulating layer surrounding the first structure (Ryu teaches, in Fig. 10, insulating layer 116 surrounding 160B).
Re: Claim 3, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
wherein an area of the first structure is larger than an area of the first electrode when viewed along the first direction (Ryu teaches, in Fig. 10, an area of 160B is larger than an area of 165A when viewed along the Z-direction; the recitation of “an area of the first structure” does not require the total projected area of the entire first structure to be larger than the total projected area of the entire first electrode, hence the relative areas illustrated by Ryu satisfies the recited area relationship).
Re: Claim 4, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
wherein the first structure is provided with a second metal film having the same composition as the first metal film (160B may comprise Tungsten (W) which has the same composition as the first metal film of first landing pad 160A).
Re: Claim 6, Ryu discloses all the limitations of claim 4 on which this claim depends.
Ryu further teaches
further comprising: a signal line in contact with the first metal film (Ryu teaches, in Fig. 10 and ¶¶ [0061] – [0062], first lower electrode 172A in contact with 160A, where 172A is a conductive structure and thus corresponds to the claimed signal line), and the first metal film and the second metal film are provided between the semiconductor device and the first insulating layer (first and second landing pads 160A and 160B are disposed between 172A and 112. Note: this limitation is interpreted as “the first metal film and the second metal film are provided between the signal line and the first insulating layer”, as explained in the rejected under 35 U.S.C. 112(b) above).
Re: Claim 7, Ryu discloses all the limitations of claim 4 on which this claim depends.
Ryu further teaches
wherein a plurality of the oxide semiconductors are two-dimensionally arranged in a first area (Ryu teaches, in Fig. 10 and ¶¶ [0036] – [0037], plurality of oxide semiconductor channel layer 130 spaced apart from each other in the X and Y directions and arranged in a matrix form), and a plurality of the first structures are two-dimensionally arranged in a second area located along an outer edge of the first area, when viewed along the first direction (Ryu teaches, in Fig. 10 and ¶ [0056], plurality of second landing pads 160B, corresponding to the first structures, spaced apart in the X and Y direction and arranged in a matrix form, including second landing pads 160B disposed in a peripheral portion of the matrix among an outer edge of the area containing the plurality of channel layers 130, when viewed along the vertical Z direction corresponding to the first direction).
Re: Claim 9, Ryu discloses all the limitations of claim 4 on which this claim depends.
Ryu further teaches
wherein the first structure includes a hole portion overlapped with the second metal film and penetrating the first insulating layer when viewed along the first direction (Ryu teaches first channel trench 112t1 formed through first interlayer insulating layer 112, thus penetrating first interlayer insulating layer 112 , with second gate electrode 150B disposed within trench 112t1, and second landing pad 160B overlapping gate electrode 150B in the Z direction. Thus, 160B overlaps at least a portion of trench 112t1 when viewed along Z. The recitation that the first structure “includes” a hole portion encompasses such an underlying associated hole portion. Accordingly, Ryu teaches the first structure 160B including hole portion 112t1, which penetrates first insulating layer 112 and overlaps second metal film 160B when viewed along the first direction).
Re: Claim 10, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
wherein the metal oxide includes indium and tin (Ryu, ¶ [0096], 165A may include indium tin oxide (ITO)).
Re: Claim 11, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
wherein the first direction is perpendicular to the second direction (Ryu teaches, in Fig. 10, Z- direction is perpendicular to X- direction).
Re: Claim 35, Ryu discloses all the limitations of claim 1 on which this claim depends.
Ryu further teaches
a semiconductor storage device comprising: the semiconductor device according to claim 1 (Ryu teaches semiconductor memory device);
a first capacitor electrode that is connected to the first electrode or the second electrode (Ryu teaches, in Fig. 10 and ¶ [0060], first lower electrode 172A of first capacitor structure 170A connected to first landing pad 160A);
a second capacitor electrode that faces the first capacitor electrode (Ryu teaches, in Fig. 10 and ¶ [0060], upper electrode 176 of first capacitor structure 170A, 176 faces 172A); and
a dielectric film that is provided between the first capacitor electrode and the second capacitor electrode (dielectric layer 174 is interposed between first lower electrode 172A and upper electrode 176).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 20220223732 A1)
Re: Claim 5, Ryu discloses all the limitations of claim 4 on which this claim depends.
Ryu further teaches
wherein the first insulating layer is provided with a first surface continuous with a contact surface between the first end and the first conductive film (Ryu teaches, in Fig. 10, upper portion of first insulating layer 112 is the claimed first surface that is continuous with a contact surface between has first contact surface between the first end of 130 that is adjacent to 150A and first conductive film 165A), the first metal film has a first thickness (160A has a first thickness), and is provided away from the first surface (160A is away from the upper portion of 112), and the second metal film has the first thickness (160B has the same first thickness as 160A), and is provided in contact with the first surface (Ryu teaches, in ¶ [0055], 160B is in contact with the upper portion of first insulating layer 112 since 160B is formed on the first interlayer insulating layer 112. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second metal film 160B is in electrical contact with 112).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 20220223732 A1) in view of Kim (US 20230171954 A1).
Re: Claim 8, Ryu discloses all the limitations of claim 7 on which this claim depends.
Ryu further teaches an electrode structure including a metal film containing the first metal atom and a conductive film containing the metal oxide and disposed between the metal film and the first insulating layer (W landing pad 160A/160B and ITO contact pattern 165A/165B disposed beneath the respective landing pad and above insulating layer 112).
Ryu silent is regarding providing a plurality of such electrode structures as dummy electrodes in the second area and arranging the plurality of first structures along an outer edge of the second area.
However, Kim teaches providing a plurality of dummy structures in a second area located along an outer edge of a first area and providing additional conductive structures along an outer side of the second area. Kim teaches, in Fig. 2 and ¶ [0039], cell pads LP disposed in cell array region CAR; dummy patterns PW disposed in a dummy region located at an edge of cell array region CAR; and peripheral landing pads PL disposed in peripheral region PR outside the dummy region. Kim further teaches that cell landing pads LP, dummy patterns PW, and peripheral landing pads PL are formed by separating a common conductive layer into individual conductive structures, wherein the conductive layer may comprise tungsten (W).
Thus, Kim teaches an arrangement in which a plurality of dummy patterns PW are provided in a dummy/second area located along an outer edge of the cell array/first area, and peripheral landing pads PL are provided along an outer side of the dummy/second area. Kim further teaches forming the dummy patterns PW and peripheral landing pads PL from the same W-containing conductive layers used to form the functional cell landing pads LP.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ryu to include Kim’s arrangement of conductive landing pads and dummy patterns, such that a plurality of dummy electrodes are provided in an edge region and the first structures are provided along an outer edge thereof. Kim teaches a known arrangement in which cell landing pads, dummy pads, dummy patterns, and peripheral landing pads are formed from conductive material, with the dummy disposed at an edge of the cell-array region and the peripheral landing pads disposed outwardly in the peripheral region. One of ordinary skill would have been motivated to apply Kim’s known edge/dummy-pattern arrangement to Ryu’s semiconductor to provide a predictable transition between the active array region and the peripheral region and to facilitate fabrication of the conductive structures using a common conductive-layer patterning scheme, as taught by Kim.
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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