Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction/Election
Applicant’s election of Group 1 drawn to claims 1-5 and 11 is acknowledged. Claims 6-10 are withdrawn from consideration.
Status of Claims
Claims 1-11 are pending.
Claims 6-10 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0057313 A1 Shiokawa (herein “Shiokawa”).
Regarding Claim 1, Shiokawa discloses:
A semiconductor device (see generally Figs. 1 and 2 showing first and second embodiments, see also Fig. 15 showing a modification of the second embodiment, reference made to second embodiment shown in Fig. 2 unless otherwise noted) comprising:
a first electrode (#41, Fig. 2);
a first insulating layer (#46b, Fig. 2) provided over the first electrode (#41) in a stacking direction (vertical direction);
a second insulating layer (#46a, Fig. 2) provided over the first insulating layer (#46b) in the stacking direction (vertical direction);
a second electrode (#45, Fig. 2) provided over the second insulating layer (#46b) in the stacking direction (vertical direction);
a gate electrode (#44, Fig. 2, [0034]) interposed between the first (#46b) and second (#46a) insulating layers in the stacking direction (vertical direction), and extending in a first direction (horizontal direction) intersecting the stacking direction (vertical direction);
a channel layer (#42a, Fig. 2, [0037]) penetrating the gate electrode (#44), extending in the stacking direction (vertical direction), having a first end (bottom end) connected to the first electrode (#41), and having a second end (top end) connected to the second electrode (#45); and
a gate insulating layer (#43a, Fig. 2) provided between the first insulating layer (#46b), the gate electrode (#44), and the second insulating layer (#46a), and the channel layer (#42a),
wherein the channel layer (#42a) has a first cross-sectional area (#C1, see comparative example shown in Fig. 5) at a height position of the first insulating layer (#46b) and a second cross-sectional area (#C2, see comparative example shown in Fig. 5) at a height position of the gate electrode (#44), the first cross-sectional area (#C1) is larger than the second cross-sectional area (#C2), and
the gate electrode (#44) has a wider width at a penetrating portion (paragraphs [0070]-[0078] disclose process of forming through hole that gate dielectric and channel layer, etch rate of lower insulating layer and disclosure of diameter of hole at various heights through thickness of device appears to be substantially identical to the instant application) of the channel layer (#42a) than any other portions in a second direction (in/out of page) intersecting the stacking direction (vertical direction) and the first direction (horizontal direction).
Regarding Claim 2, Shiokawa discloses: The semiconductor device according to claim 1,
Shiokawa further discloses:
wherein the gate electrode (#44) covers at least one of both end portions (top/bottom ends) of the channel layer (#42a) in the second direction (in/out) with a substantially uniform thickness (see Fig. 2, see formation of through hole in [0070]-[0078]).
Regarding Claim 3, Shiokawa discloses: The semiconductor device according to claim 1,
Shiokawa further discloses:
wherein the channel layer (#42a) has a third cross-sectional area (not explicitly disclosed, see annotated Fig. 5 below) at a height position of the second insulating layer (#46b), the third cross-sectional area (see annotated Fig. 5 below) is also larger than the second cross-sectional area (#C2).
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Shiokawa Fig. 5 – Annotated by Examiner
Regarding Claim 11, Shiokawa discloses:
A semiconductor device (see generally Figs. 1 and 2 showing first and second embodiments, see also Fig. 15 showing a modification of the second embodiment, reference made to second embodiment shown in Fig. 2 unless otherwise noted) comprising:
a first electrode (#41, Fig. 2);
a first insulating layer (#46b, Fig. 2) provided over the first electrode (#41) in a stacking direction (vertical direction);
a second insulating layer (#46a, Fig. 2) provided over the first insulating layer (#46b) in the stacking direction (vertical direction);
a second electrode (#45, Fig. 2) provided over the second insulating layer (#46b) in the stacking direction (vertical direction);
a gate electrode (#44, Fig. 2, [0034]) interposed between the first (#46b) and second (#46a) insulating layers in the stacking direction (vertical direction), and extending in a first direction (horizontal direction) intersecting the stacking direction (vertical direction);
a channel layer (#42a, Fig. 2, [0037]) penetrating the gate electrode (#44), extending in the stacking direction (vertical direction), having a first end (bottom end) connected to the first electrode (#41), and having a second end (top end) connected to the second electrode (#45); and
a gate insulating layer (#43a, Fig. 2) provided between the first insulating layer (#46b), the gate electrode (#44), and the second insulating layer (#46a), and the channel layer (#42a),
wherein the channel layer (#42a) has a first cross-sectional area (#C1, see comparative example shown in Fig. 5) aligned with the first insulating layer (#46b), a second cross-sectional area (#C2, see comparative example shown in Fig. 5) aligned with the gate electrode (#44), and a third cross-sectional area (see annotated Fig. 5 below) aligned with the second insulating layer, at least one of the first cross-sectional area (#C1) or the third cross-sectional area (see annotated Fig. 5 above) is larger than the second cross-sectional area (#C2), and
the gate electrode (#44) has an expanded width in a second direction (in/out of the page) intersecting the stacking direction (vertical direction) and the first direction (horizontal direction), the expanded width is wider (see Fig. 5, see also paragraphs [0070]-[0078] disclose process of forming through hole that gate dielectric and channel layer, etch rate of lower insulating layer and disclosure of diameter of hole at various heights through thickness of device appears to be substantially identical to the instant application) than any other portion of the gate electrode (#44) along the extending first direction (horizontal direction).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0057313 A1 Shiokawa in view of US 2021/0305431 A1 Ishimaru (herein “Ishimaru”).
Regarding Claim 4, Shiokawa discloses: The semiconductor device according to claim 3,
Shiokawa further discloses:
[0071]-[0074] and [0092]-[0093]. Shiokawa discloses a property of different materials having different etching rates in order to form the through-hole for the channel structure.
Shiokawa does not explicitly disclose:
further comprising: a third insulating layer provided between the gate electrode and the second insulating layer and containing a material different from a material of the first and second insulating layers.
However, in analogous art, Ishimaru teaches:
See generally Fig. 1 and [0076]-[0145] disclosing first embodiment of device.
a third insulating layer (#32, Fig. 1, [0111]) provided between the gate electrode ([0100]) and the second insulating layer (#28, [0107]) and containing a material different from a material of the first () and second insulating layers ([0106] and [0112]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Shiokawa as disclosed in paragraphs [0071]-[0074] and [0092]-[0093] and form another insulating layer above the gate electrode like taught by Ishimaru, for the purposes of etch selectivity and formation of a specific hole structure with a chosen diameter for device operation.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0057313 A1 Shiokawa
Regarding Claim 5, Shiokawa discloses: The semiconductor device according to claim 1,
Shiokawa does not explicitly disclose:
wherein the channel layer has a fourth cross-sectional area at a height position of the second insulating layer, the fourth cross-sectional area is smaller than the second cross-sectional area.
However, Shiokawa teaches:
[0071]-[0074] and [0092]-[0093]. Shiokawa discloses a property of different materials having different etching rates in order to form the through-hole for the channel structure.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the channel structure having a width near the upper insulating layer (fourth cross-sectional area) smaller than the width near the first insulating layer (second cross-sectional area). Paragraph [0098] teaches the thickness of the channel affects the connection between the lower and upper electrodes, the on-current between electrodes, as well as the resistance within the channel. Paragraphs [0071]-[0074] and [0092]-[0093] teach a property of different materials having different etching rates in order to form the through-hole for the channel structure. Therefore the width of the channel and subsequently the materials of the lower and upper insulating layers are considered result-effective variables that may be adjusted by a person of ordinary skill in the art to meet the needs of the device, in this case being a smaller width near the upper electrode and the second insulating layer to tune for a specific electrical connection or resistance value within the channel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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