DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for domestic priority based on a Provisional application 63/519,338 filed on August 14, 2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/01/2024 and 02/27/2025 are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I and Sub-Species III in the reply filed on 08/03/2026 is acknowledged. Applicant has withdrawn Claims 6, 7, 10 and 11 as being drawn to a nonelected Species/Sub-Species.
However, Claims 1-11 are allowable. Claims 6, 7, 10 and 11, withdrawn from consideration by the Applicant as a result of the restriction requirement, requires all the limitations of an allowable claim. Pursuant to the procedures set forth in MPEP § 821.04(a), the restriction requirement between Species/Sub-Species, as set forth in the Office action mailed on 06/01/2026, is hereby withdrawn and claims 6, 7, 10 and 11 hereby are rejoined and fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or non-statutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ha et al. (US 20230052477 A1).
Regarding Claim 12, the closest prior art of record, Ha et al. (US 20230052477 A1) discloses an integrated circuit device comprising:
a wimpy transistor stack TS_1 on a substrate 100, the wimpy transistor stack TS_1 comprising (see annotated Fig. 7: TS_1, 100, paragraph 0031):
a first upper transistor comprising (right stack of region R2 in Fig. 7):
a plurality of first upper channel regions USP_1 stacked in a vertical direction D3 (see annotated Fig. 7: USP_1, D3, paragraph 0035, 0036);
a first upper gate structure UE_1 in which the plurality of first upper channel regions USP_1 are provided (see annotated Fig. 7: UE_1, USP_1, paragraph 0074);
and a first upper source/drain region SD2 contacting the plurality of first upper channel regions USP_1 (see annotated Fig. 7: SD2, paragraph 0035, 0036);
and a first lower transistor (right stack of region R1 in Fig. 7) that is between the substrate 100 and the first upper transistor (right stack of region R2 in Fig. 7) and comprises:
a plurality of first lower channel regions LSP_1 that are stacked in the vertical direction D3 (see annotated Fig. 7: LSP_1, D3, paragraph 0035, 0036);
a first lower gate structure LE_1 in which the plurality of first lower channel regions LSP_1 are provided (see annotated Fig. 7: LE_1, LSP_1, paragraph 0074);
and a first lower source/drain region SD1 contacting the plurality of first lower channel regions LE_1 (see annotated Fig. 7: SD1, paragraph 0035, 0036);
and a transistor stack TS_2 adjacent to the wimpy transistor stack TS_1 on the substrate 100 (see annotated Fig. 7: TS_1, TS_2, 100, paragraph 0031), the transistor stack TS_2 comprising:
a second upper transistor (left stack of region R2 in Fig. 7) comprising:
a plurality of second upper channel regions USP_2 stacked in the vertical direction D3, wherein the first upper source/drain region SD2 contacts the plurality of second upper channel regions USP_2 (see annotated Fig. 7: USP_2, D3, SD2, paragraph 0035, 0036);
a second upper gate structure UE_2 in which the plurality of second upper channel regions are provided USP_2 (see annotated Fig. 7: UE_2, USP_2, paragraph 0074);
and a second lower transistor (left stack of region R1 in Fig. 7) that is between the substrate 100 and the second upper transistor (left stack of region R2 in Fig. 7)and comprises:
a plurality of second lower channel regions LSP_2 that are stacked in the vertical direction D3, wherein the first lower source/drain region SD1 contacts the plurality of second lower channel regions LSP_2 (see annotated Fig. 7: LSP_2, D3, SD1, paragraph 0035, 0036);
a second lower gate structure LE_2 in which the plurality of second lower channel regions are provided LSP_2 (see annotated Fig. 7: LE_2, LSP_2, paragraph 0074);
wherein a lowermost one of the plurality of first upper channel regions USP_1 and an uppermost one of the plurality of first lower channel regions LSP_1 are spaced apart from each other in the vertical direction D3 by a first distance d5, a lowermost one of the plurality of second upper channel regions USP_2 and an uppermost one of the plurality of second lower channel regions LSP_2 are spaced apart from each other in the vertical direction D3 by a second distance d6, and the first distance d5 is longer than the second distance d6 (see annotated Fig. 7: d5, d6, USP_1, USP_2, LSP_1, LSP_2).
Regarding Claim 18, Ha et al. discloses an integrated circuit device comprising:
a wimpy transistor stack TS_1 on a substrate 100, the wimpy transistor stack TS_1 comprising (see annotated Fig. 7: TS_1, 100, paragraph 0031):
a first upper transistor comprising (right stack of region R2 in Fig. 7):
a plurality of first upper channel regions USP_1 stacked in a vertical direction D3 (see annotated Fig. 7: USP_1, D3, paragraph 0035, 0036);
a first upper gate structure UE_1 in which the plurality of first upper channel regions USP_1 are provided (see annotated Fig. 7: UE_1, USP_1, paragraph 0074);
and a first upper source/drain region SD2 contacting the plurality of first upper channel regions USP_1 (see annotated Fig. 7: SD2, paragraph 0035, 0036);
and a first lower transistor (right stack of region R1 in Fig. 7)that is between the substrate 100 and the first upper transistor (right stack of region R2 in Fig. 7) and comprises:
a plurality of first lower channel regions LSP_1 that are stacked in the vertical direction D3 (see annotated Fig. 7: LSP_1, D3, paragraph 0035, 0036);
a first lower gate structure LE_1 in which the plurality of first lower channel regions LSP_1 are provided (see annotated Fig. 7: LE_1, LSP_1, paragraph 0074);
and a first lower source/drain region SD1 contacting the plurality of first lower channel regions LE_1 (see annotated Fig. 7: SD1, paragraph 0035, 0036) ;
and a transistor stack TS_2 adjacent to the wimpy transistor stack TS_1 on the substrate 100 (see annotated Fig. 7: TS_1, TS_2, 100, paragraph 0031), the transistor stack TS_2 comprising:
a second upper transistor (left stack of region R2 in Fig. 7) comprising:
a plurality of second upper channel regions USP_2 stacked in the vertical direction D3, wherein the first upper source/drain region SD2 contacts the plurality of second upper channel regions USP_2 (see annotated Fig. 7: USP_2, D3, SD2, paragraph 0035, 0036);
a second upper gate structure UE_2 in which the plurality of second upper channel regions are provided USP_2 (see annotated Fig. 7: UE_2, USP_2, paragraph 0074);
a second lower transistor (left stack of region R1 in Fig. 7) that is between the substrate 100 and the second upper transistor (left stack of region R2 in Fig. 7)and comprises:
a plurality of second lower channel regions LSP_2 that are stacked in the vertical direction D3, wherein the first lower source/drain region SD1 contacts the plurality of second lower channel regions LSP_2 (see annotated Fig. 7: LSP_2, D3, SD1, paragraph 0035, 0036);
a second lower gate structure LE_2 in which the plurality of second lower channel regions are provided LSP_2 (see annotated Fig. 7: LE_2, LSP_2, paragraph 0074);
and wherein a number of the plurality of first upper channel regions USP_1 (i.e., two) is less than a number of the plurality of second upper channel regions USP_2 (i.e., three) (see annotated Fig. 7: USP_1, USP_2, paragraph 0036), and/or a number of the plurality of first lower channel regions is less than a number of the plurality of second lower channel regions.
Regarding Claim 19, Ha et al. discloses the integrated circuit device of Claim 18, wherein the number of the plurality of first upper channel regions USP_1 (i.e., two) is less than the number of the plurality of second upper channel regions USP_2 (i.e., three), and a lower surface of a lowermost one of the plurality of first upper channel regions USP_1 is farther than a lower surface of a lowermost one of the plurality of second upper channel regions USP_2 from the substrate 100 in the vertical direction D3 (see annotated Fig. 7: USP_1, USP_2, paragraph 0036).
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Annotated Fig. 7 of Ha et al. (US 20230052477 A1)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. (US 20230052477 A1), as applied to Claim 12 above, further in view of Chiu et al. (US 20220130822 A1).
Regarding Claim 16, Ha et al. fails to explicitly teach the integrated circuit device of Claim 18, wherein the number of the plurality of first lower channel regions LSP_1 is less than the number of the plurality of second lower channel regions LSP_2.
However, Chiu et al. teaches an integrated circuit device, wherein the number of the plurality of first lower channel regions 124 ( in the region 130a of Fig. 2A) is less than the number of the plurality of second lower channel regions 124 ( in the region 130c of Fig. 2A) (see Fig. 2A: 124, paragraph 0026, 0027).
Therefore, it would have been obvious to a person or ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Ha et al. and Chiu et al. in order to have the number of the plurality of first lower channel regions be less than the number of the plurality of second lower channel regions. Doing so would enable the utilizing of different numbers of channel to provide a combination of performance and efficiency selected to provide an improved power performance area cost metric for the IC device or IC system as a whole, as recognized by Chiu et al. (see paragraph 0031).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. (US 20230052477 A1), further in view of Chiu et al. (US 20220130822 A1), as applied to Claim 16 above, further in view of Agrawal et al. (US 20230420507 A1).
Regarding Claim 17, the combination of Ha et al. and Chiu et al. fails to explicitly teach the integrated circuit device of Claim 16, wherein an upper surface of an uppermost one of the plurality of first lower channel regions is closer than an upper surface of an uppermost one of the plurality of second lower channel regions to the substrate in the vertical direction.
However, Agrawal et al. teaches an integrated circuit device, wherein an upper surface of an uppermost one of the plurality of first lower channel regions 104 (shaded regions to the left of Fig. 1A) is closer than an upper surface of an uppermost one of the plurality of second lower channel regions 106 to the substrate 102 in the vertical direction Z (Fig. 1A: 104, 106, 102, Z, paragraph 0027, 0028).
Therefore, it would have been obvious to a person or ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Ha et al., Chiu et al. and Agrawal et al., in order to have an upper surface of an uppermost one of the plurality of first lower channel regions closer than an upper surface of an uppermost one of the plurality of second lower channel regions to the substrate in the vertical direction. Doing so would facilitate the integration of the first lower channel stack and the second lower channel stack around the shared lower source/drain structure.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. (US 20230052477 A1), as applied to Claim 18 above, further in view of Chiu et al. (US 20220130822 A1) and Agrawal et al. (US 20230420507 A1).
Regarding Claim 20, Ha et al. fails to explicitly teach the integrated circuit device of Claim 18, wherein the number of the plurality of first lower channel regions is less than the number of the plurality of second lower channel regions, and an upper surface of an uppermost one of the plurality of first lower channel regions is closer than an upper surface of an uppermost one of the plurality of second lower channel regions to the substrate in the vertical direction.
However, Chiu et al. teaches an integrated circuit device, wherein the number of the plurality of first lower channel regions 124 ( in the region 130a of Fig. 2A) is less than the number of the plurality of second lower channel regions 124 ( in the region 130c of Fig. 2A) (see Fig. 2A: 124, paragraph 0026, 0027).
Therefore, it would have been obvious to a person or ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Ha et al. and Chiu et al. in order to have the number of the plurality of first lower channel regions be less than the number of the plurality of second lower channel regions. Doing so would enable the utilizing of different numbers of channel to provide a combination of performance and efficiency selected to provide an improved power performance area cost metric for the IC device or IC system as a whole, as recognized by Chiu et al. (see paragraph 0031).
Furthermore, Agrawal et al. teaches an integrated circuit device, wherein an upper surface of an uppermost one of the plurality of first lower channel regions 104 (shaded regions to the left of Fig. 1A) is closer than an upper surface of an uppermost one of the plurality of second lower channel regions 106 to the substrate 102 in the vertical direction Z (Fig. 1A: 104, 106, 102, Z, paragraph 0027, 0028).
Therefore, it would have been obvious to a person or ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Ha et al., Chiu et al. and Agrawal et al. in order to have an upper surface of an uppermost one of the plurality of first lower channel regions closer than an upper surface of an uppermost one of the plurality of second lower channel regions to the substrate in the vertical direction. Doing so would facilitate the integration of the first lower channel stack and the second lower channel stack around the shared lower source/drain structure.
Allowable Subject Matter
Claims 1-11 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, the closest prior art of record, Ha et al. (US 20230052477 A1) discloses an integrated circuit device comprising:
a wimpy transistor stack TS_1 on a substrate 100, the wimpy transistor stack TS_1 comprising (see annotated Fig. 7: TS_1, 100, paragraph 0031):
a first upper transistor comprising (right stack of region R2 in Fig. 7):
a plurality of first upper channel regions USP_1 stacked in a vertical direction D3 (see annotated Fig. 7: USP_1, D3, paragraph 0035, 0036);
a first upper gate structure UE_1 in which the plurality of first upper channel regions USP_1 are provided (see annotated Fig. 7: UE_1, USP_1, paragraph 0074);
and a first upper source/drain region SD2 contacting the plurality of first upper channel regions USP_1 (see annotated Fig. 7: SD2, paragraph 0035, 0036);
and a first lower transistor (right stack of region R1 in Fig. 7) that is between the substrate 100 and the first upper transistor (right stack of region R2 in Fig. 7) and comprises:
a plurality of first lower channel regions LSP_1 that are stacked in the vertical direction D3 (see annotated Fig. 7: LSP_1, D3, paragraph 0035, 0036);
a first lower gate structure LE_1 in which the plurality of first lower channel regions LSP_1 are provided (see annotated Fig. 7: LE_1, LSP_1, paragraph 0074);
and a first lower source/drain region SD1 contacting the plurality of first lower channel regions LE_1 (see annotated Fig. 7: SD1, paragraph 0035, 0036);
and a first intergate insulator SS_1 between the first upper gate structure UE_1 and the first lower gate structure LE_1 (see annotated Fig. 7: SS_1, UE_1, LE_1, paragraph 0046);
and a transistor stack TS_2 adjacent to the wimpy transistor stack TS_1 on the substrate 100 (see annotated Fig. 7: TS_2, 100, paragraph 0031), the transistor stack TS_2 comprising:
a second upper transistor (left stack of region R2 in Fig. 7) comprising:
a plurality of second upper channel regions USP_2 stacked in the vertical direction D3, wherein the first upper source/drain region SD2 contacts the plurality of second upper channel regions USP_2 (see annotated Fig. 7: USP_2, D3, SD2, paragraph 0035, 0036);
a second upper gate structure UE_2 in which the plurality of second upper channel regions are provided USP_2 (see annotated Fig. 7: UE_2, USP_2, paragraph 0074);
a second lower transistor (left stack of region R1 in Fig. 7) that is between the substrate 100 and the second upper transistor (left stack of region R2 in Fig. 7)and comprises:
a plurality of second lower channel regions LSP_2 that are stacked in the vertical direction D3, wherein the first lower source/drain region SD1 contacts the plurality of second lower channel regions LSP_2 (see annotated Fig. 7: LSP_2, D3, SD1, paragraph 0035, 0036);
a second lower gate structure LE_2 in which the plurality of second lower channel regions are provided LSP_2 (see annotated Fig. 7: LE_2, LSP_2, paragraph 0074);
and a second intergate insulator SS_2 between the second upper gate structure UE_2 and the second lower gate structure LE_2 (see annotated Fig. 7: SS_2, UE_2, LE_2, paragraph 0046);
wherein the first intergate insulator SS_1 is spaced apart from the second intergate insulator SS_2 in a horizontal direction D1 (see annotated Fig. 7: SS_1, SS_2, paragraph 0046),
However, the prior art of record fails to disclose, teach, suggest or render obvious the claimed limitiaions: “and the first intergate insulator overlaps a lowermost one of the plurality of second upper channel regions and/or an uppermost one of the plurality of second lower channel regions in the horizontal direction”.
Claim 2-11 are allowed due to their dependency on Claim 1.
Claim 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 13, Ha et al. teaches the integrated circuit device of Claim 12, wherein the wimpy transistor stack TS_1 further comprises a first intergate insulator SS_1 between the first upper gate structure UE_1 and the first lower gate structure LE_1 (see annotated Fig. 7: SS_1, UE_1, LE_1, paragraph 0046), the transistor stack TS_2 further comprises a second intergate insulator SS_2 between the second upper gate structure UE_2 and the second lower gate structure LE_2 (see annotated Fig. 7: SS_2, UE_2, LE_2, paragraph 0046), the first intergate insulator has a first thickness t9 in the vertical direction D3, the second intergate insulator has a second thickness t10 in the vertical direction D3 (see annotated Fig. 7: t9, t10).
However, the prior art of record fails to disclose, teach, suggest or render obvious the claimed limitiaions: “and the first thickness is thicker than the second thickness.”
Claim 14 and 15 are allowable to due to their dependency on Claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 08/14/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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