Attorney’s Docket Number: 114124-0765
Filing Date: 03/01/2024
Claimed Priority Date: 03/20/2023 (JP2023-043809)
Applicants: Kitamoto et al.
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the election filed on 06/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s elections without traverse of Group II Invention, directed semiconductor storage device, and of Species I (reading on 3-24) in the reply filed on 06/11/2026, is acknowledged. Applicant indicated that claims 1-11 read on the elected. The examiner agrees. Accordingly, claims 12-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites “an intersection of at least one of the plurality of conductive layers or the first pillar functions as a memory cell” is not written in a manner described in the disclosure, leading the claim to be indefinite. According to [0007] in the disclosure, the conductive layer and the first pillar must intersect to form a memory cell. Examiner understands the “or” to be a typographical error and for the purpose of examination, the claim will be construed as reciting -- an intersection of at least one of the plurality of conductive layers and the first pillar functions as a memory cell --- as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Claims 2-8 depend from claim 1, thus inherit the deficiencies identified supra.
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 9-11 are Allowable.
Regarding Claim 1, the closest identified prior art, Watanabe et al (US 20230284447 A1) (See e.g., Figs 2A-2E and [0060]-[0096] ) discloses a a semiconductor storage device comprising:
a stacked body (LM) having a plurality of conductive layers and a plurality of first insulating layers stacked alternately (WL and OL), the stacked body including a first region (memory region MR) and a second region ( staircase region SR);
one or more first pillars extending, in a stacking direction of the stacked body, within the first region of the stacked body (PL); and
a second pillar extending, in the stacking direction, within the second region of the stacked body (HR), wherein
each of the first and second pillars includes a semiconductor layer (CN) , a second insulating layer (TN), a third insulating layer (BK), and a fourth insulating layer (CT), and (dummy layer MEd corresponds to the memory layer ME of the pillar PL described above. Further, the dummy layers BKd, CTd, and TNd in the dummy layer MEd correspond to the block insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN of the pillar PL, respectively.)
the fourth insulating layer interposed between the second and third insulating layers, (See e.g., Figs 2C-2E)
the second insulating layer covering a sidewall of the semiconductor layer, (See e.g., Figs 2C-2E)
the fourth insulating layer covering a sidewall of the second insulating layer, the fourth insulating layer containing a different material from the second and third insulating layers, (See e.g., [0084])
the third insulating layer covering a sidewall of the fourth insulating layer , (See e.g., Figs 2C-2E)
an intersection of at least one of the plurality of conductive layers or the first pillar functions as a memory cell ([0063]), and
While Watanbe recognizes the need for preventing the columnar portion HR from coming into contact with the contact CC ([0084]) to avoid adverse interference, it does not remedy the interference problem by making the BK layer thick in the staircase region, rather by adjusting the positioning of the HR columns. Accordingly, Watanbe and does not anticipate or make obvious the following:
the third insulating layer of the second pillar is thicker than the third insulating layer of the first pillar in a plane perpendicular to the stacking direction
Regarding Claim 9, Watanbe similarly discloses most aspects of the invention as Claim 1, however it does not anticipate or make obvious the following:
the third insulating layer is thicker than the block insulating layer in a plane perpendicular to the stacking direction.
Therefore, the above limitations in the entirety of their respective claims are neither anticipated nor rendered obvious over the prior art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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