DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Species I, including claims 1-11, and 17-20 in the reply filed on December 17, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C.112, the applicant), regards as the invention.
Claim 6 depends on claim 1 but recites “the amplifier”, which is not disclosed in claim 1.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(l) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshima (US 2014/0010556A1).
Regarding claims 1 and 19, Yoshima discloses a chip interconnect (100, Fig. 1) comprising: an optical fiber coupling port (Fig.1 and [0022], the optical receiver 100 in an OLT receiving the burst signals from optical fiber; and the pin/interface where the optical burst signal enters/connects to the receiver); a photodetector (1, Fig.2) coupled to the optical fiber coupling port (see Fig.2) configured to generate an electrical signal in response to an optical signal received at the optical fiber coupling port ([0027], “The photo-detector 1 converts the burst signals … to a current signal”); a converter (22, Fig.2) coupled to receive the electrical signal and configured to generate a differential data signal based on the electrical signal (see [0030], The single-phase differential converter circuit 22 converts the single-phase voltage signal the TIA circuit 21 outputs… a differential signal); and a two-wire coupling port comprising output pins of the chip interconnect (the output of 100, Fig.2), the two-wire coupling port configured to couple the differential data signal to the output pins (see Figs. 1 and 2, the differential signal exits via the output pins of the chip interconnect to the circuit 200).
Regarding claim 2, Yoshima, as discussed in claim 1, discloses an amplifier (21, Fig.2) coupled to the photodetector (1) configured to amplify the electrical signal ( [0028], The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal) and provide the electrical signal to the converter (22)( [0030], The single-phase differential converter circuit 22 converts the single-phase voltage signal the TIA circuit 21).
Regarding claim 3, Yoshima, as discussed in claim 2, discloses the amplifier (21, Fig.2) comprising a transimpedance amplifier ([0028] “The TIA circuit 21”), and wherein the transimpedance amplifier (21) is configured to convert a current signal of the photodetector to a voltage signal as the electrical signal ([0028] “The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal”).
Regarding claim 5, Yoshima, as discussed in claim 2, disclose a controller (301, Fig.1) to regulate the amplifier (21) ([0028], “The control circuit 301 controls the conversion gain of the TIA circuit 21”).
Claims 1, 7-10, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bai et al., (US 2022/0337318 A1).
Regarding claims 1 and 19, Bai et al., disclose a chip interconnect (902, Fig.9) comprising:
an optical fiber coupling port (Fig.9, the point/pin when the optical communication channel 908 meets the receiver 902); a photodetector (904) coupled to the optical fiber coupling port ( see Fig.9) configured to generate an electrical signal in response to an optical signal received at the optical fiber coupling port ([0081], “Photodetector 904 converts these optical signals into a corresponding set of electrical signals”); a converter (906) coupled to receive the electrical signal (see Fig.9) and configured to generate a differential data signal based on the electrical signal ([0081], “These electrical signals are amplified and converted into a corresponding set of differential electrical signals by transimpedance amplifier 906”); and a two-wire coupling port comprising output pins (the output interface or pin for 942/944, Fig.9) of the chip interconnect (902), the two-wire coupling port configured to couple the differential data signal (942/944) to the output pins (see Fig.9).
Regarding claim 7, Bai et al., as discussed in claim 1, disclose the converter (906, Fig.9) drives the differential data signal (942/944) to the output pins (the output interface or pin for 942/944, and Fig.9 shows the TIA outputs the differential data signal (942/944) to pins/interface to the sink).
Regarding claim 8, Bai et al., as discussed in claim 1, disclose the output pins (output interface/pin for 942/944, Fig.9) being coupled to circuit board traces (the paths between the 902 and 930) coupled to pins of an external processing chip (930, see Fig.9).
Regarding claim 9, Bai et al., as discussed in claim 1, disclose the output pins (output pin/interface for 942/944, Fig.9) are configured to be coupled to a two-pin input port (input interface/pin for amplifier 938) for a differential data signal (942/944) of an external processing chip (930).
Regarding claim 10, Bai et al., as discussed in claim 1, disclose the chip interconnect (902, Fig.9) being formed on a single substrate (inherent include a base/substrate in which the 902 stays on) that is separate from an external processing chip (930)( Fig.9 shows the chip interconnect 902 and the processing chip 930 as separate blocks, they are distinct components connected by wires).
Regarding claim 17, Bai et al., disclose a computing system comprising:
a processing chip (930, Fig.9) configured to receive a differential data signal (RX_data+ 942/RX_data− 944) at a two-pin input port (Fig. 9, the pin for receiving the differential data signal RX_data+ 942 RX_data− 944 from the transimpedance amplifier 906) ; and a chip interconnect (902) comprising a two-wire coupling port (see Fig. 9, the pin for carrying the 942/944) configured to couple the differential data signal (942/944) to the two-pin input port of the processing chip (930),
the chip interconnect (902) further comprising: an optical fiber coupling port (the interface on the optical communication channel 908) coupled to an optical fiber (908) and configured to receive an optical signal from a data source through the optical fiber ([0081], “receives one or more HDMI optical signals via optical communication channel 908”); a photodetector
(904) coupled to the optical fiber coupling port and configured to generate an electrical signal based on the optical signal at the optical fiber coupling port ([0081], “Photodetector 904 converts these optical signals into a corresponding set of electrical signals”);and a converter (906) coupled to receive the electrical signal (see Fig.9) and configured to generate the differential data signal based on the electrical signal ([0081], “These electrical signals are amplified and converted into a corresponding set of differential electrical signals by transimpedance amplifier 906”) and coupled to the two-wire coupling port to provide the differential data signal to the two-wire coupling port (Fig.9, output of 906 to 942/944).
Regarding claim 18, Bai et al., as discussed in claim 17, disclose a substrate (the base of the 902) to carry the chip interconnect (902, Fig.9) independent of the processing chip (930)(Fig.9 shows the chip interconnect 902 and the processing chip 930 as separate blocks, they are distinct components connected by wires).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshima in view of Barany et al. (US 2024/0039578 A1).
Regarding claim 4, Yoshima, as discussed in claim 1, do not disclose the amplifier comprising an equalizer, and wherein the equalizer is configured to precondition the electrical signal before amplifying the electrical signal as claimed. Barany et al., disclose amplifier (114, Fig.1) comprising an equalizer (112), and wherein the equalizer is configured to precondition the electrical signal before amplifying the electrical signal ([0027], “the first shaping circuit 112 may shape the signal… In this way, the signal is equalized or “flattened” prior to reaching the amplifier 114). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshima, by utilizing the teaching of Barany et al., to optimize signal quality prior to amplification.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al., in view of Kumar (US 9,425,999 B1).
Regarding claim 6, Bai et al., as discussed in claim 1, do not disclose a serializer coupled to an amplifier, wherein the serializer is configured to convert the electrical signal to a differential data signal as claimed. Kumar discloses a serializer (610, Fig.6,) coupled to the amplifier configured to convert the electrical signal to a differential data signal (col.8, lines39-42, “the receiver equalizer (640) is the equalizer (100) described with respect to FIG. 1. As such, the output signals (162, 167) provide a conditioned differential serialized signal). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., by utilizing the teaching of Kumar, to prevent/reduce distortion that would occur if the amplifier received unconditional signals, improving the transmission of different signals.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al.,
Regarding claim 11, although Bai et al., as discussed in claim 1, do not explicitly disclose a substrate and wherein the photodetector and the converter are formed on the substrate as claimed, Bai et al., disclose HDMI optical receiver 902 further including a photodetector 904, a transimpedance amplifier TIA 906 (paragraph [0079]), showing a base or substrate for these components. However, if not, using a substrate and wherein the photodetector and the converter are formed on the substrate would have been obvious to one of ordinary skill in the art for providing a compact design for the system. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., accordingly to provide compact design for the system, allowing the circuit to compensate more accurately.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshima, in view of Kumar (US 9,425,999 B1).
Regarding claim 20, Yoshima as discussed in claim 19, disclose the generating the differential data signal comprising converting the electrical signal from a current signal of the photodetector to a voltage signal ([0028]-[0030], “The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal, and outputs it as an output signal” and “differential converter circuit 22 converts the single-phase voltage signal the TIA circuit 21 outputs… to as a differential signal”). Yoshima does not disclose
serializing the voltage signal to the differential data signal as claimed.
Kumar discloses a serializer (610, Fig.6) coupled to the amplifier (equalizer 620, “equalizer with the frequency response curve (500) may generate an amplifier boost”, col. 8, lines 3-5), wherein the serializer (610) is configured to convert the electrical signal (col.8, lines 18-19. “the serializer device (610) transforms into a single serialized data signal”) to a differential data signal (col.8, lines 41-42 “the output signals… may provide a conditioned differential serialized signal”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshima, by utilizing the teaching of Kumar, to prevent/reduce distortion that would occur if the amplifier received unconditional signals, improving the transmission of different signals.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm.
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/M.T.T./Examiner, Art Unit 2878
/THANH LUU/Primary Examiner, Art Unit 2878