DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/28/2026 has been entered.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 17, 18, 26, 27, 29, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Royle et al. (US 2008/0063395 A1) in view of Bai et al., (US 2022/0337318 A1).
Regarding claims 17 and 30, Royle et al., disclose (Figs. 2-5) a computing system comprising:
a processing chip (18/21/40/60) comprising a plurality of two-pin input ports ( Rx1+ and Rx1−, and Rx2+ and Rx2−, see Fig. 3, the SERDES chip 21 has multiple differential channels Rx1+ and Rx1−, and Rx2+ and Rx2− constitutes as the plurality of two-pin input ports),
each two-pin input port (Rx1+ and Rx1−) configured to receive a respective differential data signal (see Figs. 3-5, and [0022] show the two-pin input port Rx1+ and Rx1− receiving differential data signals); and
a plurality of chip interconnects (26, 27 or 45, 46, 47), wherein the plurality of chip interconnects (26, 27 or 45, 46, 47) are configured to couple to different types of data sources having different electrical interfaces (these transceiver modules are with different interfaces such as receiving signal at different wavelength from different external optical data sources, see [0020], “the first transceiver module 26, which includes a transmitter 28 for transmitting a signal at a first wavelength, e.g. 1550 nm”, and “the second transceiver module 27, which includes a transmitter 29 for transmitting a signal at a second wavelength, e.g. 1310 nm”)
, each chip interconnect (26/27 or 45/46/47) comprising a two-wire coupling port configured to couple the respective differential data signal to the corresponding one of the plurality of two-pin input ports (see Fig.3, the transceiver module 26/27 has a differential output port comprising the Rx1+ and Rx1−, forming a two-wire coupling port that route the output signal to the SERDES transceiver chip 21),
the chip interconnect (26/27/45/46/47) further comprising: an optical fiber coupling port coupled to an optical fiber (32a/55a, Figs.3-4 or 12a, Fig. 2) and configured to receive an optical signal from a respective data source of the data sources through the optical fiber (see Fig.3),
a photodetector (receiver 30/31, or 52/54, see Figs.3-5 and [0006], “The receiver side includes a photodetector 16, e.g. PIN or APD receiver”) coupled to the optical coupling port (coupled to the input optical connector 32a/55a, see Figs. 3-4 or 12a, Fig. 2)
and configured to generate an electrical signal based on the optical signal at the optical fiber coupling port ([0006], [0020], “The receiver side includes a photodetector 16, e.g. PIN or APD receiver, which converts a 10 Gb/s input optical signal to an input electrical signal”).
Although Royle et al., disclose a converter (inherently included, see [0006]) coupled to receive the electrical signal and configured to generate the differential data signal based on the electrical signal, and coupled to the two-wire coupling port to provide the differential data signal to the two-wire coupling port (the converter is inherently included because [0006] shows that, “a CDR 17, which cleans up the input electrical signal before sending it to a SERDES 18” or see Fig. 3, and [0020], there would be a circuit/converter within the receivers 30/31 so that it receives the photodetector electrical outputs, generates differential signals such as Rx1+ and Rx1−, and outputs the differential signal to two-wire coupling port coupled to the SERDES input port/pin); however, if not, Bai et al., disclose a converter (1408/1412/1416, Fig. 14) coupled to receive the electrical signal and configured to generate the differential data signal based on the electrical signal, and coupled to the two-wire coupling port to provide the differential data signal to the two-wire coupling port (Fig.14 show the 1408/1412/1416 takes the signal from the photodiode and converts it into a differential signal pair down to output wires). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., by utilizing the teaching of Bai et al., to prevent/reduce distortion and overall system noise prevention.
Regarding claim 18, Royle et al., in view of Bai et al., as discussed in claim 17, Royle et al., disclose (Figs. 2-5) a substrate (the base or inherently included to hold the interconnect components) to carry the plurality of chip interconnects independent of the processing chip (SERDES 18/21/40/60).
Regarding claim 26, Royle et al., in view of Bai et al., as discussed in claim 17, Royle et al., do not disclose the converter of the chip interconnect driving the respective differential data signal to the two-wire coupling port as claimed. Bai et al., disclose the converter (1408/1412/1416, Fig.14) drives the respective differential data signal to the two-wire coupling port (Fig.14 show the 1408/1412/1416 takes the signal from the photodiode and converts it into a differential signal pair down to output wires). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., by utilizing the teaching of Bai et al., to prevent/reduce distortion and overall system noise prevention.
Regarding claim 27, Royle et al., in view of Bai et al., as discussed in claim 17, Royle et al., disclose (Figs. 3-5) the two- wire coupling port of the chip interconnect (Rx1+ and Rx1−, Rx2+ and Rx2−) being coupled to the corresponding one of the plurality of two-pin input ports of the processing chip (18/21/40/60). Royle et al., do not disclose the circuit board traces as claimed. Bai et al., disclose he two-wire coupling port of the chip interconnect (1402, Fig.14 or Fig. 9) is coupled to the corresponding one of the plurality of two-pin input ports of the processing chip (the HDMI sink) via circuit board traces (the paths between the receiver 902 and the sink 930), or [0123], “the optical receiver 1402 transmits the TMDS0+/− through TMDS3+/−electrical signal as a differential electrical signal (e.g., as differential signal pair RX_data+ 942 and RX_data− 944). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., by utilizing the teaching of Bai et al., to provide better optical path connection.
Regarding claim 29, although Royle et al., in view of Bai et al., as discussed in claim 17, do not explicitly disclose a substrate and wherein the photodetector and the converter are formed on the substrate as claimed, However, using a substrate and wherein the photodetector and the converter are formed on the substrate would have been obvious to one of ordinary skill in the art for providing a compact design for the system. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., in view of Bai et al., accordingly, to provide compact design for the system, allowing the circuit to compensate more accurately.
5. Claims 21, 22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Royle et al., in view of Bai et al., further in view of Yoshima (US 2014/0010556A1).
Regarding claims 21-22, 24, Royle et al., in view of Bai et al., as discussed in claim 17, do not disclose an amplifier coupled to the photodetector configured to amplify the electrical signal and provide the electrical signal to the converter as claimed. Yoshima, as discussed in claim 1, discloses an amplifier (21, Fig.2) coupled to the photodetector (1) configured to amplify the electrical signal ( [0028], The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal) and provide the electrical signal to the converter (22)( [0030], The single-phase differential converter circuit 22 converts the single-phase voltage signal the TIA circuit 21). Yoshima also discloses the amplifier (21, Fig.2) comprising a transimpedance amplifier ([0028] “The TIA circuit 21”), and wherein the transimpedance amplifier (21) is configured to convert a current signal of the photodetector to a voltage signal as the electrical signal ([0028] “The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal”), and a controller (301, Fig.1) to regulate the amplifier (21) ([0028], “The control circuit 301 controls the conversion gain of the TIA circuit 21”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., in view of Bai et al., by utilizing the teaching of Yoshima, for more stable voltage signal, getting better noise prevention for the overall system.
6. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Royle et al., in view of Bai et al., in view of Yoshima and further in view of Barany et al. (US 2024/0039578 A1).
Regarding claim 23, Royle et al., in view of Bai et al., and Yoshima, as discussed in claim 21, do not disclose the amplifier comprising an equalizer configured to precondition the electrical signal before amplifying the electrical signal as claimed. Barany et al., disclose amplifier (114, Fig.1) comprising an equalizer (112), and wherein the equalizer is configured to precondition the electrical signal before amplifying the electrical signal ([0027], “the first shaping circuit 112 may shape the signal… In this way, the signal is equalized or “flattened” prior to reaching the amplifier 114). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., in view of Bai et al and Yoshima, by utilizing the teaching of Barany et al., to optimize signal quality prior to amplification.
7. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Royle et al., in view of Bai et al., in view of Yoshima and further in view of Kumar (US 9,425,999 B1).
Regarding claim 25, Royle et al., in view of Bai et al., and Yoshima, as discussed in claim 21, do not disclose a serializer coupled to an amplifier, configured to convert the electrical signal to a respective differential data signal as claimed. Kumar discloses a serializer (610, Fig.6,) coupled to the amplifier configured to convert the electrical signal to a differential data signal (col.8, lines39-42, “the receiver equalizer (640) is the equalizer (100) described with respect to FIG. 1. As such, the output signals (162, 167) provide a conditioned differential serialized signal). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., in view of Bai et al. and Yoshima, by utilizing the teaching of Kumar, to prevent/reduce distortion that would occur if the amplifier received unconditional signals, improving the transmission of different signals.
8. Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Royle et al., in view of Bai et al., in view of Victor et al., (US 2004/0080285 A1).
Regarding claim 28, Royle et al., in view of Bai et al., as discussed in claim 17, do not disclose a demultiplexer as claimed. Victor et al., disclose a demultiplexer (“a demultiplexer”, [0095]) configured to convert a respective differential data signal ([0095], “Typical multiplexing and demultiplexing techniques involve the use of high-speed digital serial lines over low-voltage differential signal trace pairs”) into a parallel format for a parallel bus ([0095], “A demultiplexer is a device that takes data from a high-speed serial data line, and translates the signal onto a lower-speed parallel bus”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Royle et al., in view of Bai et al., by utilizing the teaching of Victor et al., to better minimizing degradation across the system.
Response to Arguments
9. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)-272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm.
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/M.T.T./Examiner, Art Unit 2878
/THANH LUU/Primary Examiner, Art Unit 2878
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