CTFR 18/593,184 CTFR 97054 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. This Office Action is in response to amendments and remarks filed 04/15/2026. Claims 17, 18, 21-30 are currently pending. Claim Rejections - 35 USC § 112 07-30-02 AIA 3. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 4. Claims 21-27 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C.112, the applicant), regards as the invention. Regarding claims 21-27 and 29, the terms “(Recaptures Claim…)” is improper and doesn’t make sense. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless - 07-08-aia AIA (a)(l) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 17, 18, 26, 27, 30 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Bai et al., (US 2022/0337318 A1) . Regarding claims 17 and 30 , Bai et al., disclose (Figs. 8-14) a computing system comprising: a processing chip (an HDMI sink, see Figs. 8, 14 and [0123], “TMDS RX 1408 transmits the TMDS0+/− electrical signal as a differential electrical signal (e.g., as differential signal pair RX_data+ 942 and RX_data− 944) to an HDMI sink (e.g., sink 808) comprising a plurality of two-pin input ports , each two-pin input port configured to receive a respective differential data signal (inherently includes, see Fig. 4, the receiver 1402 includes four different pairs of differential signals, TMDS0+/− through TMDS3+/−, connecting to the HDMI sink. The input terminals on the sink’s internal chip for the TMDS signals inherently includes two-pin input ports to receive the differential data pairs); and a plurality of chip interconnects (1402, Fig.14 shows the receiver 1402 routing four separation, parallel differential lines/connects) each chip interconnect comprising a two-wire coupling port (the output interface or pin for 942/944, Fig.9) configured to couple the respective differential data signal to the corresponding one of the plurality of two-pin input ports (Figs. 9, 14 and [0123] “transmits the TMDS0+/− electrical signal as a differential electrical signal (e.g., as differential signal pair RX_data+ 942 and RX_data− 944) to an HDMI sink”), the chip interconnect further comprising: an optical fiber coupling port ( Fig.14, the point/pin when the optical communication channel meets the receiver ) coupled to an optical fiber (see [0113] and [0122], “optical receiver 1402 may receive TMDS0+/− optical signal 1312 via optical communication channel 1310” and [0113], “each of optical communication channel 1310 through 1334 is implemented using one or more optical fibers, and comprises a unidirectional optical communication channel”) and configured to receive an optical signal from a data source through the optical fiber (Figs. 8, 14 and [0121], the optical receiver 1402 interfaces with the optical communication channels to receive high-speed signals; and [0091], “photodetector 1004 receives one or more HDMI optical signals via optical communication channel 1008”. Also, the receiver or photodetector where it takes in light from the channel including the optical fiber coupling port. This port receives optical signals generated by a data source as shown in Fig. 8); a photodetector (1406/1410/1414/1418, Fig.14) coupled to the optical fiber coupling port and configured to generate an electrical signal based on the optical signal at the optical fiber coupling port ([0122]-[0123, PD 1406 converts these optical signals into a corresponding set of electrical signals); and a converter (1408/1412/1416, Fig. 14) coupled to receive the electrical signal and configured to generate the differential data signal based on the electrical signal, and coupled to the two-wire coupling port to provide the differential data signal to the two-wire coupling port (Fig.14 show the 1408/1412/1416 takes the signal from the photodiode and converts it into a differential signal pair down to output wires). Regarding claim 18 , Bai et al., as discussed in claim 17, disclose (Fig.10) a substrate (the base or inherently included to hold the interconnect components) to carry the plurality of chip interconnects independent of the processing chip (sink) (Fig.10 shows the plurality of chip interconnects (the receiver) and the sink as separate blocks, they are distinct components connected by wires). Regarding claim 26 , Bai et al., as discussed in claim 17, disclose the converter (1408/1412/1416, Fig.14) drives the respective differential data signal to the two-wire coupling port (Fig.14 show the 1408/1412/1416 takes the signal from the photodiode and converts it into a differential signal pair down to output wires). Regarding claim 27 , Bai et al., as discussed in claim 17, disclose the two-wire coupling port of the chip interconnect (1402, Fig.14 or Fig. 9) is coupled to the corresponding one of the plurality of two-pin input ports of the processing chip (the HDMI sink) via circuit board traces (the paths between the receiver 902 and the sink 930), or [0123], “the optical receiver 1402 transmits the TMDS0+/− through TMDS3+/−electrical signal as a differential electrical signal (e.g., as differential signal pair RX_data+ 942 and RX_data− 944) to an HDMI sink (e.g., sink 808)”) . Claim Rejections - 35 USC § 103 07-20-aia AIA 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al., in view of Victor et al., (US 2004/0080285 A1) . Regarding claim 28 , Bai et al., as discussed in claim 17, do not disclose a demultiplexer as claimed. Victor et al., disclose a demultiplexer (“a demultiplexer”, [0095]) configured to convert a respective differential data signal ([0095], “Typical multiplexing and demultiplexing techniques involve the use of high-speed digital serial lines over low-voltage differential signal trace pairs”) into a parallel format for a parallel bus ([0095], “A demultiplexer is a device that takes data from a high-speed serial data line, and translates the signal onto a lower-speed parallel bus”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., by utilizing the teaching of Victor et al., to better minimizing degradation across the system . 07-21-aia AIA Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al ., Regarding claim 29 , although Bai et al., as discussed in claim 17, do not explicitly disclose a substrate and wherein the photodetector and the converter are formed on the substrate as claimed, Bai et al., disclose HDMI optical receiver further including a photodetector, a transimpedance amplifier TIA (paragraph [0079]), showing a base or substrate for these components. However, if not, using a substrate and wherein the photodetector and the converter are formed on the substrate would have been obvious to one of ordinary skill in the art for providing a compact design for the system. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., accordingly to provide compact design for the system, allowing the circuit to compensate more accurately . 07-21-aia AIA Claim s 21, 22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Bai et al., in view of Yoshima (US 2014/0010556A1) . Regarding claims 21-22, 24 , Bai et al., as discussed in claim 17, do not disclose an amplifier coupled to the photodetector configured to amplify the electrical signal and provide the electrical signal to the converter as claimed. Yoshima, as discussed in claim 1, discloses an amplifier (21, Fig.2) coupled to the photodetector (1) configured to amplify the electrical signal ( [0028], The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal) and provide the electrical signal to the converter (22)( [0030], The single-phase differential converter circuit 22 converts the single-phase voltage signal the TIA circuit 21). Yoshima also discloses the amplifier (21, Fig.2) comprising a transimpedance amplifier ([0028] “The TIA circuit 21”), and wherein the transimpedance amplifier (21) is configured to convert a current signal of the photodetector to a voltage signal as the electrical signal ([0028] “The TIA circuit 21 converts the current signal passing through the conversion by the photo-detector 1 to a voltage signal”), and a controller (301, Fig.1) to regulate the amplifier (21) ([0028], “The control circuit 301 controls the conversion gain of the TIA circuit 21”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., by utilizing the teaching of Yoshima, for more stable voltage signal, getting better noise prevention for the overall system . 07-21-aia AIA Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al., in view of Yoshima, and further in view of Barany et al. (US 2024/0039578 A1) . Regarding claim 23 , Bai et al., in view of Yoshima, as discussed in claim 21, do not disclose the amplifier comprising an equalizer configured to precondition the electrical signal before amplifying the electrical signal as claimed. Barany et al., disclose amplifier (114, Fig.1) comprising an equalizer (112), and wherein the equalizer is configured to precondition the electrical signal before amplifying the electrical signal ([0027], “the first shaping circuit 112 may shape the signal… In this way, the signal is equalized or “flattened” prior to reaching the amplifier 114). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshima in view of Bai et al., by utilizing the teaching of Barany et al., to optimize signal quality prior to amplification . 07-21-aia AIA Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Bai et al., in view of Yoshima, and further in view of Kumar (US 9,425,999 B1) . Regarding claim 25 , Bai et al., in view of Yoshima, as discussed in claim 21, do not disclose a serializer coupled to an amplifier, configured to convert the electrical signal to a respective differential data signal as claimed. Kumar discloses a serializer (610, Fig.6,) coupled to the amplifier configured to convert the electrical signal to a differential data signal (col.8, lines39-42, “the receiver equalizer (640) is the equalizer (100) described with respect to FIG. 1. As such, the output signals (162, 167) provide a conditioned differential serialized signal). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bai et al., in view of Yoshima , by utilizing the teaching of Kumar, to prevent/reduce distortion that would occur if the amplifier received unconditional signals, improving the transmission of different signals . Response to Arguments 07-37 AIA 7. Applicant's arguments filed 04/15/2026 have been fully considered but they are not persuasive as detailed below: Applicant states “Bai does not teach or suggest "a plurality of chip interconnects, each chip interconnect comprising a two-wire coupling port configured to couple the respective differential data signal to the corresponding one of the plurality of two-pin input ports”. Examiner respectfully disagrees and points out that Fig. 14 explicitly discloses the multi-channel parallel interconnects for the limitation “a plurality of chip interconnects”. Bai discloses in Fig.14 channel 1: comprises an optical signal 1312, PD 1406, and converter 1408, driving a two-wire differential port; channel 2: comprises an optical signal 1320, PD 1410, and converter 1412, driving a second two-wire differential port; channel 3: comprises an optical signal 1328, PD 1414, and converter 1416, driving a third two-wire differential port; channel 4: comprises an optical signal 1336, PD 1418, and converter 1420, driving a fourth two-wire differential port. Next for the limitation “each chip interconnect comprising a two-wire coupling port configured to couple the respective differential data signal to the corresponding one of the plurality of two-pin input ports”. Bai discloses in paragraphs [0121-[0123] and Fig.8, each of the fourth channels above delivers different data to a designated input on the downstream HDMI sink. For instance, see [0123], “TMDS RX 1408 transmits the TMDS0+/− electrical signal as a differential electrical signal (e.g., as differential signal pair RX_data+ 942 and RX_data− 944) to an HDMI sink (e.g., sink 808)”. In order to accept the different signal pairs, the HDMI sink inherently includes two-pin input ports such as pins/interfaces for receiving the differential data signal RX_data+ 942 RX_data− 944. Since the cited reference, Bai discloses "a plurality of chip interconnects, each chip interconnect comprising a two-wire coupling port configured to couple the respective differential data signal to the corresponding one of the pluralities of two-pin input ports”. Therefore, the rejection above is proper . Conclusion 07-40 AIA 8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)-272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, GEORGIA EPPS can be reached on (571)-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visithttps://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.T.T./Examiner, Art Unit 2878 /THANH LUU/Primary Examiner, Art Unit 2878 Application/Control Number: 18/593,184 Page 2 Art Unit: 2878 Application/Control Number: 18/593,184 Page 3 Art Unit: 2878 Application/Control Number: 18/593,184 Page 4 Art Unit: 2878 Application/Control Number: 18/593,184 Page 5 Art Unit: 2878 Application/Control Number: 18/593,184 Page 6 Art Unit: 2878 Application/Control Number: 18/593,184 Page 7 Art Unit: 2878 Application/Control Number: 18/593,184 Page 8 Art Unit: 2878 Application/Control Number: 18/593,184 Page 9 Art Unit: 2878 Application/Control Number: 18/593,184 Page 10 Art Unit: 2878 Application/Control Number: 18/593,184 Page 11 Art Unit: 2878
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