CTNF 18/593,300 CTNF 100442 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-14 pending. Claims 15-20 cancelled. Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the electroplating layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Note, see 112(b) rejection of claims 5-6 drawn to an electroplating layer below. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claims 5-6, claim 5 recites the phrase “ wherein the first heat dissipation part is coupled to the flexible substrate through an electroplating layer ”. As can be seen in the drawings, specifically in reference to Fig. 3 or the originally filed drawings, it appears that an additional layer does not exist between the substrate and the first heat dissipating portion. Therefore, it is unclear which of the following is being claimed: (1) an additional layer lies between the two respective layers (see drawings objection above), or (2) the first heat dissipating layer is the electroplating layer. Additionally, the claimed element “ the electroplating layer ” is also unclear, as it appears to be claiming product and process characteristics, as electroplating is the method in which the layer is produced along with the presence of the layer itself. The element should instead be referenced as the electroplated layer , as the process of deposition/formation should not be claimed and should instead be referenced without an active process like electroplating being implied. MPEP 2113 states the patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." See MPEP 2113. Therefore, the claim will be interpreted under the second (2) interpretation listed above as to be consistent with the specification and drawings, wherein the first heat dissipation layer is the electroplated layer, consistent with the cross-sectional view shown in Fig. 3. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-5, 7, and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342437 A1 Huang et al ( herein “Huang” ) in view of US 2021/0193549 A1 Eid et al ( herein “Eid” ) . Regarding Claim 1, Huang discloses : A chip package ( see generally cross-sectional view in Fig. 6 ) comprising: a flexible substrate (#110, see [0024]: “In the embodiment of the heat-dissipation structure 130/140 being applied to the chip on plastic package, the heat-dissipation structure 130/140 may be attached to a flexible plastic substrate where the chip is mounted and cover the at least a part of the chip.”) comprising: a bottom surface (#114); a side wall ( left/right sides ); and a top surface (#112) comprising a central region ( portion overlapped by die structure 124 if taken from a top-down view, see annotated Fig. 6 below ) and an edge region ( portion not overlapped by die structure 124 if taken from a top-down view ) around the central region; a first heat dissipation part (#140) comprising: a body part ( see annotated Fig. 6 below ); and a wing part ( see annotated Fig. 6 below, herein #WP ) on the bottom surface of the flexible substrate (#110) and extending from opposite ends of the body part to the top surface of the flexible substrate, the wing part (#WP) covering the edge region of the top surface of the flexible substrate (#110); a semiconductor chip (#124) on the top surface of the flexible substrate (#110); a second heat dissipation part (#130) covering an upper surface of the semiconductor chip (#124), and a portion of the wing part (#WP) of the first heat dissipation part (#140) that covers the edge region) of the top surface of the flexible substrate (#110); and a heat dissipation glue (#135, see [0004]: “a heat dissipation sheet is normally attached to a top surface of the base film to cover the whole chip or attached to a bottom surface of the base film opposite to the chip using thermal conductive glue after the chip is electrically connected to the film via bumps.” ) on a lower surface of the second heat dissipation part (#140, specifically heat dissipation layer #136 ), wherein the heat dissipation glue (#135) connects the semiconductor chip (#124) to the second heat dissipation part (#136); Huang does not explicitly disclose : a wing part on the bottom surface of the flexible substrate and extending from opposite ends of the body part to the top surface of the flexible substrate along the side wall of the flexible substrate; wherein the heat dissipation glue connects the semiconductor chip to the second heat dissipation part and connects the second heat dissipation part to the first heat dissipation part, to form a heat dissipation path. However, in analogous art, Eid teaches : See generally interchangeable embodiments shown in Figs. 4A, 4B, 4C, and 5, specifically see Fig. 4A for reference numerals. a wing part ( see annotated Fig. 4A below ) on the bottom surface of the flexible substrate (#410) and extending from opposite ends of the body part ( see annotated Fig. 4A below ) to the top surface of the flexible substrate along the side wall of the flexible substrate ( see annotated Fig. 4A below, wrap around heat spreader (WAHS) extends from bottom surface of the substrate to the top surface of the substrate and extends over the side walls of the substrate ); wherein the heat dissipation glue (#433, TIM at interface between integrated heat spreader #451 and WAHS, see [0028]: “TIMs disclosed herein may be any suitable TIM materials, such as solder or polymer TIMs, or adhesives with high thermal conductivities (e.g., metal filled epoxies).” ) connects the semiconductor chip (#440) to the second heat dissipation part (#451) and connects the second heat dissipation part (#450, [0044]) to the first heat dissipation part (#420, [0049]-[0057]), to form a heat dissipation path ( see interfaces in annotated Fig. 4A below ). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Eid to the device disclosed by Huang and extend the heat spreader around the substrate, i.e. include a wrap-around heat spreader (WAHS) to assist in routing thermal energy away from the semiconductor chip(s) to improve device performance. Doing so would provide a direct thermal pathway from the integrated heat spreader (HIS) on the top surface of the device to the bottom surface of the device. PNG media_image1.png 706 732 media_image1.png Greyscale Huang Fig. 6 – Annotated by Examiner PNG media_image2.png 642 1053 media_image2.png Greyscale Eid Fig. 4A – Annotated by Examiner Regarding Claim 2, Huang in view of Eid discloses : The chip package of claim 1, Huang further discloses : wherein the second heat dissipation part (#130) comprises: a central portion ( see annotated Fig. 6 above ); and an edge portion ( see annotated Fig. 6 above ), wherein the heat dissipation glue (#135) is provided between the central portion ( see annotated Fig. 6 above ) and the upper surface of the semiconductor chip (#120), and wherein the heat dissipation glue (#135) is provided between the edge portion ( see annotated Fig. 6 above ) and a portion of the first heat dissipation part (#140, under the combination previously disclosed, the heat spreader wraps around the substrate ). Note, under the broadest reasonable interpretation the adhesive layer 135 lies between the second heat dissipating element 130 and the first dissipating element 140 with the substrate also disposed therein which also reads on the claim in addition to the cited rejection under the previously disclosed combination of references. Regarding Claim 3, Huang in view of Eid discloses : The chip package of claim 2, Eid further teaches : wherein the top surface of the flexible substrate further comprises: a peripheral region ( border around package substrate from a top-down view ) around the edge region; and a trench ( space occupied by WAHS from a top-down view, see annotated Fig. 3A below ) in the peripheral region at two sides of the flexible substrate, and wherein the wing part of the first heat dissipation part passes through the trench in a vertical direction, and then is bent in a horizontal direction to cover the edge region of the top surface of the flexible substrate ( see WAHS #120 in Fig. 4A, see also annotated Fig. 4A above ). Note, as currently disclosed, the cross-sectional space occupied by the wing part of the first heat dissipating part in the originally filed drawings can be considered a trench, which is consistent with the claimed limitation above. The wrap around heat spreader in the cited reference appears to be substantially identical in structure from a top-down view, and from a cross-sectional view as stated above. However, the originally filed drawings lack a cross-sectional view showing an opening in the substrate (a trench) similar to the top-down view shown in Fig. 6B, therefore it is unclear whether such an opening exists that would read on the limitation as currently claimed, which appears to be the intended interpretation. PNG media_image3.png 564 800 media_image3.png Greyscale Eid Fig. 3A – Annotated by Examiner Regarding Claim 4, Huang in view of Eid discloses : The chip package of claim 1, Huang further discloses : wherein the heat dissipation glue (#142, second adhesive layer, see also TIM layer #131/132 in Eid, see also Eid [0028] ) is further provided between the flexible substrate (#110) and the first heat dissipation part (#140). Regarding Claim 5, Huang in view of Eid discloses : The chip package of claim 1, wherein the first heat dissipation part (#140) is coupled to the flexible substrate (#110) through an electroplated layer ( first heat dissipation layer #140 ). Note, see 112(b) rejection of claim 5 above. Under the broadest reasonable interpretation based on the originally filed drawings, the first heat dissipation layer is the electroplated layer. Regarding Claim 7, Huang in view of Eid discloses : The chip package of claim 1, Huang further discloses : wherein each of the first heat dissipation part (#140) and the second heat dissipation part (#130) comprises a metal (see paragraphs [0028] and [0030]). Regarding Claim 9, Huang in view of Eid discloses : The chip package of claim 3, Huang further discloses : wherein the flexible substrate (#110) comprises: a base film (#110) comprising a flexible material ([0024]); a wiring layer (#118, [0024]), on an upper surface of the base film (#110); and a solder resist (#119, [0024]) covering the wiring layer (#118). Regarding Claim 10, Huang in view of Eid discloses : The chip package of claim 9, Huang further discloses : wherein the solder resist (#119) is provided in the central region ( see annotated Fig. 6 above ) and the edge region ( see annotated Fig. 6 above ), and is not provided in the peripheral region ( not shown in peripheral region in top-down views shown in Figs. 4 and 5 ). Regarding Claim 11, Huang in view of Eid discloses : The chip package of claim 9, Huang further discloses : wherein the upper surface of the semiconductor chip (#120) is a passive surface ( see annotated Fig. 6 above ), wherein a lower surface of the semiconductor chip (#120) is an active surface ( see annotated Fig. 6 above ), and wherein the semiconductor chip (#120) is connected to the wiring layer via a conductive bump on the active surface ( see annotated Fig. 6 above ). Note, see MPEP 2112.01, Huang in view of Eid discloses an identical structure as the present disclosure and would therefore exhibit the identical property of having an active lower surface connected to the electrical bumps, specifically, as seen in Fig. 6 the patterned circuit layer connected to the chip through electrical bumps (see [0004]) which would therefore make the bottom surface an active surface and the top surface a passive surface, as no electrical bumps are connected to the upper surface. Regarding Claim 12, Huang in view of Eid discloses : The chip package of claim 11, Huang further discloses : wherein an underfill material is between the semiconductor chip and the flexible substrate ( see [0025]: “…A filling material such as resin may be filled between the chip 120, the base film 110 and the heat-dissipation structure 130 to further fix the position of the chip 120…” ), and wherein the underfill material is around the conductive bump ( see Fig, 6 ). Regarding Claim 13, Huang in view of Eid discloses : The chip package of claim 1, Huang further discloses : wherein the first heat dissipation part (#140) does not contact the semiconductor chip (#120). Regarding Claim 14, Huang in view of Eid discloses : The chip package of claim 13, Huang further discloses : wherein a portion of the first heat dissipation part (#140) is separated from the side wall of the semiconductor chip (#120) in a horizontal direction ( see Fig. 6 ) . 07-21-aia AIA Claim s 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342437 A1 Huang et al in view of US 2021/0193549 A1 Eid et al and further in view of US 2019/0393137 A1 Yandoc et al ( herein “Yandoc” ) . Regarding Claim 6, Huang in view of Eid discloses : The chip package of claim 6, Huang in view of Eid does not explicitly disclose : wherein a thickness of the electroplating layer ( first heat dissipation part # 140) is in a range of 25 μm to 35 μm. However, in analogous art, Yandoc teaches : [0051]: “…The increased thickness of the heat sink portion 107 may result in increased thermal mass and thus improved heat sinking capability of the clip frame structure.” Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider applying the teachings of Yandoc to the device disclosed by Huang in view of Eid and form the first heat dissipating portion in a range of 25 µm to 35 µm. As Yandoc discloses, the thickness of a heat sink (heat dissipating structure) is directly responsible for the heat sinking capability of the layer, and is therefore considered a result effective variable that may be adjusted by a person of ordinary skill to meet the needs of the specific device, which in this case is tuning the thickness of the heat dissipating layer for an optimal heat dissipating capability for the device. Regarding Claim 8, Huang in view of Eid discloses : The chip package of claim 6, Huang in view of Eid does not explicitly disclose : wherein a thickness of the first heat dissipation part (#140) is in a range of 25 μm to 35 μm. However, in analogous art, Yandoc teaches : [0051]: “…The increased thickness of the heat sink portion 107 may result in increased thermal mass and thus improved heat sinking capability of the clip frame structure.” Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider applying the teachings of Yandoc to the device disclosed by Huang in view of Eid and form the first heat dissipating portion in a range of 25 µm to 35 µm. As Yandoc discloses, the thickness of a heat sink (heat dissipating structure) is directly responsible for the heat sinking capability of the layer, and is therefore considered a result effective variable that may be adjusted by a person of ordinary skill to meet the needs of the specific device, which in this case is tuning the thickness of the heat dissipating layer for an optimal heat dissipating capability for the device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/593,300 Page 2 Art Unit: 2812 Application/Control Number: 18/593,300 Page 3 Art Unit: 2812 Application/Control Number: 18/593,300 Page 4 Art Unit: 2812 Application/Control Number: 18/593,300 Page 5 Art Unit: 2812 Application/Control Number: 18/593,300 Page 6 Art Unit: 2812 Application/Control Number: 18/593,300 Page 7 Art Unit: 2812 Application/Control Number: 18/593,300 Page 8 Art Unit: 2812 Application/Control Number: 18/593,300 Page 9 Art Unit: 2812 Application/Control Number: 18/593,300 Page 10 Art Unit: 2812 Application/Control Number: 18/593,300 Page 11 Art Unit: 2812 Application/Control Number: 18/593,300 Page 12 Art Unit: 2812
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