Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the election/restriction filed on 06/15/2026, the applicant elected invention I, claims 1-18 without traverse. Claims 1-18 are examined upon the merits below. Claims 19 and 20 are withdrawn.
Claim Objections
Claim 15 is objected to because of the following informalities: it recites the limitation of “the first direction” without introducing “a first direction.” Appropriate correction is required, specifically changing language to “a first direction.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-13, 15-16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakashiba et al (US 20220238651).
Nakashiba et al teaches
[claim 1] A semiconductor device, comprising: a semiconductor substrate having an upper face and a lower face, the upper face being opposite of the lower face in a first direction (figure 4, paragraph 0045, where element ‘SUB’ is the semiconductor substrate, and the upper surface is element ‘FS’ and the lower surface is element ‘SS,’ where the upper and lower surface are opposite one another in the first direction [y-direction]),
the semiconductor substrate including: a first end portion near a first edge of the semiconductor substrate, a second end portion near a second edge of the semiconductor substrate (figures 1 and 4, paragraph 0045, where the first end portion is the portion from the left-hand side R1 to R2, and the second end portion is the portion from the right-hand side of the substrate to the line R1, and the first edge is the left-hand side edge of figure 1, and the second edge is the right-hand side edge of figure 1),
the first edge and the second edge being separated from each other in a second direction orthogonal to the first direction (figure 4, paragraph 0045, where the first end is the left-hand side end and the second end is the right-hand side end, where the two ends are separated in the second direction [x-direction] which is perpendicular to the first direction [y-direction]),
an element region between the first end portion and the second end portion in the second direction (figure 4, paragraph 0045, where the element region is the region spanned by the top gate element as designated by length ‘R2,’ called the cell region),
a first ridge portion that protrudes in the first direction from a first portion that is between the first end portion and the element portion in the second direction, the first ridge portion being on the lower face and extending along the lower face in a third direction perpendicular to the first direction and the second direction (figures 1 and 4, paragraphs 0044-0046, where the first ridge portion that protrudes in the first direction [y-direction] is the portion of the substrate between lines R1 and R2 on the left-hand side, it extends from the lower face and also extends in a third direction [direction into the page] as seen in figure 1 where it extends in the y-direction in figure 1, which is perpendicular to the first and second directions),
and a second ridge portion that protrudes in the first direction from a second portion that is between the second end portion and the element portion in the second direction, the second ridge portion being on the lower face and extending along the lower face in the third direction (figures 1 and 4, paragraphs 0044-0046, where the second ridge portion that protrudes in the first direction [y-direction] is the portion of the substrate between R1 and R2 on the right-hand side of the substrate, it extends from the lower face and also extends in a third direction [direction into the page] as seen in figure 1 where it extends in the y-direction in figure 1, which is perpendicular to the first and second directions),
[claim 2] The semiconductor device according to claim 1, wherein the semiconductor substrate is substantially rectangular in planar shape when viewed from the first direction (figure 4, paragraphs 0044-0046, where the substrate is rectangular when viewed from the first direction [y-direction], best seen in figure 1 where the substrate is a square).
[claim 3] The semiconductor device according to claim 2, wherein the first edge extends in the third direction, the second edge extends in parallel with first edge (figure 1, paragraph 0044, where the first edge [left-hand side edge of figure 1] extends in the third direction [vertical direction of figure 1 which corresponds to a direction into the page of figure 4], and the second edge [right-hand side edge of figure 1] runs parallel to the first edge),
and the semiconductor substrate further includes: a third edge extending in the second direction and meeting the first edge at a first corner and the second edge at a second corner, and a fourth edge extending in the second direction and meeting the first edge at a third corner and the second edge at a fourth corner (figure 1, paragraph 0044, where the bottom edge of figure 1 is the third edge and connects the first edge [left-hand side edge] and second edge [right-hand side edge] at a first and second corner [bottom left and bottom right corners respectively], and a fourth edge is the top edge of figure 1 and extends in a second direction and connects a first edge [left-hand side of figure 1] and second edge [right-hand side edge of figure 1] at a third and fourth corner [top left-hand corner and top right-hand corner, respectively]).
[claim 5] The semiconductor device according to claim 3, wherein the first ridge portion extends from the third edge to the fourth edge (figures 1 and 4, paragraphs 0044-0046, where the first ridge extends from the bottom edge [third edge] to the top edge [fourth edge], as seen by cross section IV present in figure 4 which runs the whole length [vertical direction] of figure 1).
[claim 6] The semiconductor device according to claim 3, wherein the lower surface of the semiconductor substrate between the first ridge portion and the second ridge portion is substantially flat from the third edge to the fourth edge (figures 1 and 4, paragraphs 0044-0046, where the first ridge and second ridge portion are flat on the bottom part from the third edge [bottom edge of figure 1] to the fourth edge [top edge of figure 1]).
[claim 7] The semiconductor device according to claim 1, wherein the first ridge portion extends parallel to the first edge from an outermost edge of the semiconductor substrate to an opposite outermost edge of the semiconductor substrate (figures 1 and 4, paragraphs 0044-0046, where the first ridge and second ridge [as shown by figure 1 below]
[claim 8] The semiconductor device according to claim 1, wherein the first ridge portion extends parallel to the first edge but an end of the first ridge portion is offset in the third direction from an outermost edge of the semiconductor substrate (figures 1 and 4, paragraph 0044-0046, where the first ridge portion [portion between elements R1 and R2, run parallel to the first edge [left-hand side edge] and is offset in the third direction [y-direction in figure 1] from the outermost edge of the semiconductor substrate by a distance of the edge of the substrate to line R1).
[claim 9] The semiconductor device according to claim 1, further comprising: a first electrode on the lower face of the semiconductor substrate; and a second electrode on the upper face of the semiconductor substrate covering the element portion (figures 1 and 4, paragraph 0044, where the first electrode [EL3] is on the lower surface of the semiconductor substrate, and the second electrode [EL1] is on an upper surface of the semiconductor substrate covering the elemental portion [known as the cell region]).
[claim 10] The semiconductor device according to claim 9, wherein a thickness of the element portion is less than a summed total of a thickness of the first portion and the first ridge portion along the first direction (figure 4, paragraph 0044, where the thickness of the elemental portion [portion of the substrate under length R2 of figure 4] has less thickness than the first portion nd the first ridge portion along the y-direction of figure 4 [first direction]).
[claim 11] The semiconductor device according to claim 9, wherein the first electrode is a continuous film on the element portion, the first ridge portion, the second ridge portion, the first end portion, and the second end portion (figure 4, paragraph 0044, where element EL3 is a continuous electrode on the lower surface of the substrate over the element portion, first and second ridge portions and the first and second edge portions).
[claim 12] The semiconductor device according to claim 11, further comprising: a conductive connecting material connecting the first electrode to a conductive member below the semiconductor substrate in the third direction (figure 29, paragraph 0108, where element LF (DP) is the leadframe/die pad and is made of a conductive material [copper, copper alloy etc..] and runs along the third direction [direction into the page of figure 29]).
[claim 13] The semiconductor device according to claim 12, wherein the first electrode includes a first conductive region that covers the element portion, a second conductive region that covers the first ridge portion, and a third conductive region that covers the first end portion, and the connecting material contacts the first conductive region, the second conductive region, and the third conductive region (figure 29, paragraph 0108, where element LF (DP) is the conductive connecting material and runs along the entire bottom surface of the substrate including the first ridge portion, the first end portion and the element region [see figure 1 below], designated into the first, second and third conductive regions).
[claim 15] A semiconductor device, comprising: a semiconductor substrate having a first electrode on a lower face and a second electrode on an upper face (figures 1 and 4, paragraphs 0044-0046, where element SUB is the substrate, element EL3 is the first electrode on the lower surface [element SS] and a second electrode, element EL1 on an upper surface [element FS]);
and a conductive member joined to the lower face by a conductive material (figures 29, paragraph 0108, where element LF (DP) is the conductive member joined to the lower face [element FS] through the bottom electrode [element EL3]),
wherein the semiconductor substrate has: a first end region near a first outer edge of the semiconductor substrate, a second end region near a second outer edge of the semiconductor substrate, the first outer edge and the second outer edge being separated from each other in a second direction orthogonal to the first direction (figures 1 and 4, paragraphs 0044-0046, where the semiconductor substrate has a first end region on the left-hand side of figure 4 near an outer region of the semiconductor substrate which runs a distance R1 from the left-hand side of the substrate. The semiconductor substrate has a second end region on the right-hand side of figure 4 near an outer region of the semiconductor substrate which runs a distance R1 from the right-hand side of the substrate. Each end region is separated by a distance in the second region, where the second direction is the x-direction of figure 4),
an element region between the first end region and the second end region in the second direction (figure 4, paragraphs 0044-0046, where the element region is the portion designated by distance R2 in the substrate denoted as the cell region),
a first ridge between the first end region and the element portion, the first ridge extending along the lower face in a third direction perpendicular to the first direction and the second direction (figures 1 and 4, paragraphs 0044-0046, where the first ridge region [as shown in figure 1 below] is situated between the element portion and the first end region and extends along a lower face in a third direction [direction into the page of figure 1, y-direction of figure 1] which is perpendicular to the first direction [y-direction of figure 1] and second direction [x-direction of figure 1]),
and a second ridge between the second end region and the element portion in the second direction, the second ridge extending along the lower face in the third direction (figures 1 and 4, paragraphs 0044-0046, where the second ridge region [as shown in figure 1 below] is situated between the element portion and the second end region and extends along a lower face in a third direction [direction into the page of figure 1, y-direction of figure 1] which is perpendicular to the first direction [y-direction of figure 1] and second direction [x-direction of figure 1]).
[claim 16] The semiconductor device according to claim 15, wherein the first electrode is a metal film covering the lower face of the semiconductor substrate including the first ridge, the second ridge, the first end region, and the second end region (figure 4, paragraph 0055, where element EL3 is the first electrode made of a metal film [through sputtering] covering the lower face [element FS] of the semiconductor substrate including the first ride, second ridge, first end and second end regions).
[claim 18] The semiconductor device according to claim 15, wherein the first ridge and the second ridge extend along the lower face of the semiconductor substrate in the third direction for the full dimension of the semiconductor substrate in the third direction (figures 1 and 4, paragraphs 0044-0046, where the first and second ridge portions [as shown in figure 1 below] extend along a third direction [into the page in figure 4 corresponding to the y-direction in figure 1] along the lower face of the semiconductor substrate for the full dimension in the third direction [the entirety of the substrate of figure 1]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakashiba et al (US 20220238651).
Nakashiba et al teaches all of the limitations of the parent claim, claim 3, but does not specifically disclose
[claim 4] The semiconductor device according to claim 3, wherein the first edge is equal in length to the second edge, the first edge is longer than the third edge, and the first edge is longer than the fourth edge.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Nakashiba et al to modify the third and fourth edge length such that the first edge is longer than the third and fourth (creating a rectangle instead of a square) for a specific use case of the particular semiconductor substrate requiring specific size requirements.
Regarding claims 14 and 17,
Nakashiba et al teaches all of the limitations of the parent claims, claims 1 and 15, but does not specifically disclose
[claim 14] The semiconductor device according to claim 1, wherein the lower face of the semiconductor substrate is substantially flat at all positions between the first ridge portion and the second ridge portion in the second direction.
[claim 17] The semiconductor device according to claim 15, wherein the lower face of the semiconductor substrate is substantially flat at all positions between the first ridge and the second ridge in the second direction.
However, a different embodiment of Nakashiba et al does teach
[claim 14] The semiconductor device according to claim 1, wherein the lower face of the semiconductor substrate is substantially flat at all positions between the first ridge portion and the second ridge portion in the second direction (figure 20, paragraph 0079, where the lower face of the semiconductor substrate is substantially flat between the first ridge portion [defined by the corner where theta of figure 4 equals 90 degrees]).
[claim 17] The semiconductor device according to claim 15, wherein the lower face of the semiconductor substrate is substantially flat at all positions between the first ridge and the second ridge in the second direction (figure 20, paragraph 0079, where the lower face of the semiconductor substrate is substantially flat between the first ridge portion [defined by the corner where theta of figure 4 equals 90 degrees]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Nakashiba et al with another embodiment of Nakashiba et al to create a flat portion between the first and second ridge portion (where theta of figure 4 becomes 90 degrees) to etch along a certain plain of the silicon substrate to maximize the manufacturing process.
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Figure 1: From figure 4 of Nakashiba et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsunami (US 11121034), Dumka (US 20210098340), He et al (US 10641824), Iguchi (US 9577032), Alie et al (US 20180369862) as similar semiconductor substrates with electrodes on both sides.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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