Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over.
Regarding claim 1, Kim discloses a semiconductor package (Fig. 1) comprising:
a wiring structure (100) including a plurality of through electrodes (a pair of 125) extending through the wiring structure and a plurality of heat dispersion through electrodes (a different pair of 125. Note: This pair of 125 is composed of matter, and therefore at least some amount of thermal conduction must occur through it. Accordingly, it must have “heat dispersion” relative to something. See additional remarks and citations below regarding “heat dispersion” as it relates to these structures and other associated structures.) extending through the wiring structure;
a semiconductor chip (200) on the wiring structure;
a plurality of terminals (250) bonding the wiring structure to the semiconductor chip (physical and electrical bonding is shown),
the plurality of terminals including a plurality of internal terminals (a pair of 250, corresponding to the pair of 125) and
a plurality of internal heat dispersion terminals (a different pair of 250, corresponding to the different pair of 125),
each of the plurality of internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the semiconductor chip ([0072]: “electrically, connect”. Note: an electrical connection must necessarily include at least one of signal/power/ground; [0121]: “electrical signals” teaches electrical connections associated with the package include at least signals), and
each of the plurality of internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the semiconductor chip (250 is composed of matter and included between 100 and 200, therefore at least some amount of thermal conduction must occur through it. Accordingly, it must necessarily “disperse heat” to some extent, in at least some operating conditions. MPEP 2112 (III).);
a high thermal conductivity layer (255. Note: This layer is composed of matter, and therefore it must necessarily have some amount of thermal conductivity greater than a vacuum, thus it has a “high thermal conductivity” relative to something. Additionally, Kim teaches 255 is configured as an underfill [0089]: “inter-chip molding material” which is consistent with Applicant’s disclosure [28] “may include an underfill”. Further, the claim as written reasonably includes materials with a wide range of thermal conductivity, thus the claimed “high” configuration does not establish a relation to any particular structure or range distinct from Kim: 255.) between the wiring structure and the semiconductor chip; and
an encapsulator (160) on the high thermal conductivity layer and contacting the semiconductor chip,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar (illustrated as exactly coplanar),
the plurality of through electrodes are connected to the plurality of internal terminals (physical and electrical connection is shown), and the plurality of heat dispersion through electrodes are electrically connected to at least a portion of the plurality of internal heat dispersion terminals (electrical connection is shown), and
the plurality of heat dispersion through electrodes and the plurality of internal heat dispersion terminals, including the plurality of internal heat dispersion terminals electrically connected to the plurality of heat dispersion through electrodes are configured not to provide any of the signal transmission, the power supply, or the grounding for the semiconductor chip.
Illustrated below is a marked and annotated figure of Fig. 1 of Kim.
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Kim teaches the heat dispersion through electrodes and corresponding terminals. However, Kim fails to teach the claimed functional configuration of these electrodes and terminals: “the plurality of heat dispersion through electrodes and the plurality of internal heat dispersion terminals, including the plurality of internal heat dispersion terminals electrically connected to the plurality of heat dispersion through electrodes are configured not to provide any of the signal transmission, the power supply, or the grounding for the semiconductor chip”.
Seo discloses a semiconductor package (Fig. 4) comprising:
a wiring structure (110) including a plurality of through electrodes (some of 118; three are illustrated; [0073]: “at least one” reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) extending through the wiring structure and a plurality of heat dispersion through electrodes (others of 118; three are illustrated; [0073]: “at least one” reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) extending through the wiring structure;
a semiconductor chip (130) on the wiring structure;
a plurality of terminals (120) bonding the wiring structure to the semiconductor chip ([0052]: “connecting portion”),
the plurality of terminals including a plurality of internal terminals (a pair of 120, corresponding to the pair of 118; three are illustrated; [0073]: “at least one” refers to a corresponding structure and reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) and
a plurality of internal heat dispersion terminals (a different pair of 120, corresponding to the different pair of 118; three are illustrated; three are illustrated; [0073]: “at least one” refers to a corresponding structure and reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes),
each of the plurality of internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the semiconductor chip ([0052]: “The second connecting portion 120 may be in a ground or floated state” in combination with [0073]: “The second connecting portion 120…to connect…to the second via 118”), and
each of the plurality of internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the semiconductor chip ([0073]: “dissipated to the outside”);
[…]
the plurality of through electrodes are connected to the plurality of internal terminals (physical and electrical connection is shown), and the plurality of heat dispersion through electrodes are electrically connected to at least a portion of the plurality of internal heat dispersion terminals (electrical connection is shown), and
the plurality of heat dispersion through electrodes and the plurality of internal heat dispersion terminals, including the plurality of internal heat dispersion terminals electrically connected to the plurality of heat dispersion through electrodes are configured not to provide any of the signal transmission, the power supply, or the grounding for the semiconductor chip (citing “Some” of [0066]: “Some or all of these heat-conducting vias may be electrically separate from circuitry of the semiconductor chip 130 that transmits signals to, from, or through the semiconductor chip 130” in combination with [0073]: “to connect the first via 135 to the second via 118”).
Modifying the semiconductor package of Kim by having at least some of the through electrodes and terminals (i.e., Kim: the “heat dispersion through electrodes” and “internal heat dispersion terminals”) functionally configured solely for heat dispersion purposes (per the teachings of Seo) would arrive at the claimed terminal and through electrode configuration. The teachings of Seo are applicable to the teachings of Kim because in each situation a chip is disposed above the wiring substrate and the chip is connected by terminals to through electrodes within the wiring substrate (Seo: Fig. 4: chip 130, wiring substrate 110, terminals 150, through electrodes 118; Kim: Fig. 1: chip 200, wiring substrate 100, terminals 250, through electrodes 125). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating the heat dispersion configuration of Seo (i.e., a functional configuration) with the structures of Kim because Seo teaches heat dispersion configuration is an additional or alternative functional configuration of an otherwise similar structure ([0066]: “Some”). MPEP 2143 (I)(D): Applying a Known Technique to a Known Device.
Seo provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed heat dispersion configuration in that it would enhance heat dispersion of the package, thereby providing enhanced functional characteristics ([0073]: “dissipated to the outside”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal and through electrode configuration because it would enhance functional characteristics of the package. MPEP 2143 (I)(G): Teaching/Suggestion/Motivation.
Illustrated below is Fig. 4 of Seo.
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Regarding claim 2, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein an upper surface of the encapsulator (See annotated figure) includes a flat portion substantially parallel to the upper surface of the wiring structure (See annotated figure) and an inclined portion between the flat portion and the semiconductor chip (See annotated figure, showing a completely vertically inclined sidewall. Note: “between” is based on a Z height, without a Z direction overlap.).
Regarding claim 3, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the plurality of internal heat dispersion terminals extend through the high thermal conductivity layer (all 250 extend through at least a portion of 255 in the Z direction).
Regarding claim 5, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein each of the plurality of internal heat dispersion terminals includes the same material as the plurality of internal terminals (Kim singularly describes the collection of 250 in [0072] without any differing properties required; thus, the collection of 250 reasonably includes “the same material”).
Regarding claim 6, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the plurality of internal heat dispersion terminals are spaced apart from the plurality of internal terminals (spaced apart by intervening 255).
Regarding claim 7, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein each of the plurality of internal heat dispersion terminals has the same size as the plurality of internal terminals (Kim singularly describes the collection of 250 in [0072] without any differing properties required, thus the collection of 250 reasonably includes the same size).
Regarding claim 9, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein at least one of the plurality of internal heat dispersion terminals is not connected to either the plurality of through electrodes or the plurality of heat dispersion through electrodes (“either…or” as claimed encompasses internal heat dispersion terminals connected to heat dispersion through electrodes when separately and distinctly grouped from the through electrodes. The structures have been cited above as separate and distinct groupings, thus meeting the claim).
Regarding claim 10, Kim in view of Seo discloses a semiconductor package (Kim: Fig. 1), further comprising: a plurality of external terminals on a lower surface of the wiring structure and connected to the plurality of through electrodes (a pair of 150 corresponding to the pair of 150, electrically connected through intervening 117; [0038]: “electrically connected to the first TSVs”).
Regarding claim 11, Kim in view of Seo discloses the semiconductor package of claim 10 (Kim: Fig. 1), further comprising a plurality of external heat dispersion terminals on the lower surface of the wiring structure and connected to the plurality of heat dispersion through electrodes (a different pair of 150 corresponding to the different pair of 150, electrically connected through intervening 117; [0038]: “electrically connected to the first TSVs”. Note: these terminals of Kim would function in the same way as Seo: Fig. 4: terminals 120, because Seo teaches the “heat dispersion” function applies in an alternative situation to an otherwise similar structure [0052]: “a heat-connecting portion”.).
Regarding claim 12, Kim in view of Seo discloses the semiconductor package of claim 11 (Kim: Fig. 1), wherein each of the plurality of external heat dispersion terminals includes the same material as the plurality of external terminals (Kim singularly describes the collection of 150 in [0117] without any differing properties required, thus the collection of 150 reasonably includes the same material).
Regarding claim 13, Kim in view of Seo discloses the semiconductor package of claim 11 (Kim: Fig. 1), wherein each of the plurality of external heat dispersion terminals has the same size as the plurality of external terminals (Kim singularly describes the collection of 150 in [0117] without any differing properties required, thus the collection of 150 reasonably includes the same size).
Regarding claim 14, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the high thermal conductivity layer fills a space between the plurality of internal terminals and the plurality of internal heat dispersion terminals (255 is spatially intervening between the pair of 250 and the different pair of 250).
Regarding claim 21, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the semiconductor package is configured such that heat generated by an operation of the semiconductor chip is externally dissipated out of the semiconductor chip through the plurality of heat dispersion through electrodes (Seo: [0073]: “The first via 135, the second connecting portion 120, and the second via 118 may dissipate heat generated in the lower semiconductor chip 130 to the outside”).
Regarding independent claim 15, Kim discloses a semiconductor package (Fig. 1) comprising:
a wiring structure (100) including a plurality of first through electrodes (a pair of 125) extending through the wiring structure and a plurality of first heat dispersion through electrodes (a different pair of 125. Note: This pair of 125 is composed of matter, and therefore at least some amount of thermal conduction must occur through it. Accordingly, it must have “heat dispersion” relative to something. See additional remarks and citations below regarding “heat dispersion” as it relates to these structures and other associated structures.) extending through the wiring structure;
a first semiconductor chip (200) on the wiring structure;
a plurality of first terminals (250) bonding the wiring structure to the first semiconductor chip (physical and electrical bonding is shown),
the plurality of first terminals including a plurality of first internal terminals (a pair of 250, corresponding to the pair of 125) and
a plurality of first internal heat dispersion terminals (a different pair of 250, corresponding to the different pair of 125),
each of the plurality of first internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the first semiconductor chip ([0072]: “electrically, connect”. Note: an electrical connection must necessarily include at least one of signal/power/ground; [0121]: “electrical signals” teaches electrical connections associated with the package include at least signals), and
each of the plurality of first internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the first semiconductor chip (250 is composed of matter and included between 100 and 200, therefore at least some amount of thermal conduction must occur through it. Accordingly, it must necessarily “disperse heat” to some extent, in at least some operating conditions. MPEP 2112 (III).) and not to provide at least one of the signal transmission, the power supply, or the grounding for the first semiconductor chip;
a second semiconductor chip (300) on the first semiconductor chip;
a plurality of second terminals (350) including
a plurality of second internal terminals (a pair of 350) between the first semiconductor chip and the second semiconductor chip, and
a first high thermal conductivity layer (255. Note: This layer is composed of matter, and therefore it must necessarily have some amount of thermal conductivity greater than a vacuum, thus it has a “high thermal conductivity” relative to something. Additionally, Kim teaches 255 is configured as an underfill [0089]: “inter-chip molding material” which is consistent with Applicant’s disclosure [28] “may include an underfill”. Further, the claim as written reasonably includes materials with a wide range of thermal conductivity, thus the claimed “high” configuration does not establish a relation to any particular structure or range distinct from Kim: 255.) between the wiring structure and the first semiconductor chip; and
an encapsulator (160) on the first high thermal conductivity layer,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar (illustrated as exactly coplanar) and
wherein the first high thermal conductivity layer covers an upper surface of the wiring structure (255 directly covers some of 100) and side surfaces of the first semiconductor chip (255 bulges beyond 200, thus it meets and covers the edge of the side surfaces, and indirectly covers additional portions of the side surfaces),
the plurality of first through electrodes are connected to the plurality of first internal terminals (physical and electrical connection is shown), and the plurality of first heat dispersion through electrodes are electrically connected to at least a portion of the plurality of first internal heat dispersion terminals (electrical connection is shown), and
the plurality of first heat dispersion through electrodes and the plurality of first internal heat dispersion terminals, including the plurality of first internal heat dispersion terminals connected to the plurality of first heat dispersion through electrodes, are configured not to provide the signal transmission, the power supply, or the grounding for the first semiconductor chip.
Kim teaches the first heat dispersion through electrodes and corresponding terminals. However, Kim fails to teach “each of the plurality of first internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the first semiconductor chip and not to provide at least one of the signal transmission, the power supply, or the grounding for the first semiconductor chip” and “the plurality of first heat dispersion through electrodes and the plurality of first internal heat dispersion terminals, including the plurality of first internal heat dispersion terminals connected to the plurality of first heat dispersion through electrodes, are configured not to provide the signal transmission, the power supply, or the grounding for the first semiconductor chip”.
Seo discloses a semiconductor package (Fig. 4) comprising:
a wiring structure (110) including a plurality of first through electrodes (some of 118; three are illustrated; [0073]: “at least one” reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) extending through the wiring structure and a plurality of first heat dispersion through electrodes (others of 118; three are illustrated; [0073]: “at least one” reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) extending through the wiring structure;
a first semiconductor chip (130) on the wiring structure;
a plurality of first terminals (120) bonding the wiring structure to the first semiconductor chip ([0052]: “connecting portion”),
the plurality of first terminals including a plurality of first internal terminals (a pair of 120, corresponding to the pair of 118; three are illustrated; [0073]: “at least one” refers to a corresponding structure and reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes) and
a plurality of first internal heat dispersion terminals (a different pair of 120, corresponding to the different pair of 118; three are illustrated; three are illustrated; [0073]: “at least one” refers to a corresponding structure and reasonably encompasses differing numbers of through electrodes, such as 4. MPEP 2144.04 (VI)(B): Duplication of Parts and MPEP 2144.05: Similar Ranges as applied to the number of electrodes),
each of the plurality of first internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the first semiconductor chip ([0052]: “The second connecting portion 120 may be in a ground or floated state” in combination with [0073]: “The second connecting portion 120…to connect…to the second via 118”), and
each of the plurality of first internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the first semiconductor chip ([0073]: “dissipated to the outside”) and not to provide at least one of the signal transmission, the power supply, or the grounding for the first semiconductor chip (citing “Some” of [0066]: “Some or all of these heat-conducting vias may be electrically separate from circuitry of the semiconductor chip 130 that transmits signals to, from, or through the semiconductor chip 130” in combination with [0073]: “to connect the first via 135 to the second via 118”);
[…]
the plurality of first through electrodes are connected to the plurality of first internal terminals (physical and electrical connection is shown), and the plurality of first heat dispersion through electrodes are electrically connected to at least a portion of the plurality of first internal heat dispersion terminals (electrical connection is shown), and
the plurality of first heat dispersion through electrodes and the plurality of first internal heat dispersion terminals, including the plurality of first internal heat dispersion terminals connected to the plurality of first heat dispersion through electrodes, are configured not to provide the signal transmission, the power supply, or the grounding for the first semiconductor chip (citing “Some” of [0066]: “Some or all of these heat-conducting vias may be electrically separate from circuitry of the semiconductor chip 130 that transmits signals to, from, or through the semiconductor chip 130” in combination with [0073]: “to connect the first via 135 to the second via 118”).
Modifying the semiconductor package of Kim by having at least some of the through electrodes and terminals (i.e., Kim: the “first heat dispersion through electrodes” and “first internal heat dispersion terminals”) functionally configured solely for heat dispersion purposes (per the teachings of Seo) would arrive at the claimed terminal and through electrode configuration. The teachings of Seo are applicable to the teachings of Kim because in each situation a chip is disposed above the wiring substrate and the chip is connected by terminals to through electrodes within the wiring substrate (Seo: Fig. 4: chip 130, wiring substrate 110, terminals 150, through electrodes 118; Kim: Fig. 1: chip 200, wiring substrate 100, terminals 250, through electrodes 125). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating the heat dispersion configuration of Seo (i.e., a functional configuration) with the structures of Kim because Seo teaches heat dispersion configuration is an additional or alternative functional configuration of an otherwise similar structure ([0066]: “Some”). MPEP 2143 (I)(D): Applying a Known Technique to a Known Device.
Seo provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed heat dispersion configuration in that it would enhance heat dispersion of the package, thereby providing enhanced functional characteristics ([0073]: “dissipated to the outside”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal and through electrode configuration because it would enhance functional characteristics of the package. MPEP 2143 (I)(G): Teaching/Suggestion/Motivation.
Regarding claim 16, Kim in view of Seo discloses the semiconductor package of claim 15 (Kim: Fig. 1), wherein the first semiconductor chip includes a plurality of second through electrodes extending through the first semiconductor chip and connected to the plurality of first internal terminals (a pair of 225 corresponding to the pair of 250, at least physically connected through intervening 217).
Regarding claim 17, Kim in view of Seo discloses the semiconductor package of claim 16 (Kim: Fig. 1), wherein the plurality of second internal terminals are connected to the plurality of second through electrodes (illustrated as connected).
Regarding claim 18, Kim in view of Seo discloses the semiconductor package of claim 16 (Kim: Fig. 1), wherein at least one of the plurality of first internal heat dispersion terminals is not connected to either the plurality of first through electrodes or the plurality of first heat dispersion through electrodes (“either…or” as claimed encompasses first internal heat dispersion terminals connected to first heat dispersion through electrodes when separately and distinctly grouped from the first through electrodes. The structures have been cited above as separate and distinct groupings, thus meeting the claim), wherein the first semiconductor chip includes a plurality of second heat dispersion through electrodes extending through the first semiconductor chip and connected to the plurality of first internal heat dispersion terminals (a different pair of 225 corresponding to the different pair of 250, at least physically connected through intervening 217).
Regarding claim 19, Kim in view of Seo discloses the semiconductor package of claim 18 (Kim: Fig. 1), further comprising a plurality of second internal heat dispersion terminals between the first semiconductor chip and the second semiconductor chip (a different pair of 350), wherein the plurality of second internal heat dispersion terminals are connected to the plurality of second heat dispersion through electrodes and spaced apart from the plurality of second internal terminals (illustrated as connected, spaced apart by intervening 355).
Regarding claim 20, Kim in view of Seo discloses the semiconductor package of claim 15 (Kim: Fig. 1), further comprising a second high thermal conductivity layer between the first semiconductor chip and the second semiconductor chip (355), wherein the first semiconductor chip is surrounded by the first high thermal conductivity layer and the second high thermal conductivity layer (at least partially surrounding the upper and lower surfaces of 200), and wherein the encapsulator is on the second high thermal conductivity layer (160 is directly on 355) and spaced apart from the first semiconductor chip (at least a portion of 160 is spaced apart from a portion of 200 by intervening 255).
Regarding claim 22, Kim in view of Seo discloses the semiconductor package of claim 15 (Kim: Fig. 1), wherein the semiconductor package is configured such that heat generated by an operation of the first semiconductor chip is externally dissipated out of the first semiconductor chip through the plurality of first heat dispersion through electrodes (Seo: [0073]: “The first via 135, the second connecting portion 120, and the second via 118 may dissipate heat generated in the lower semiconductor chip 130 to the outside”).
Response to Arguments
Applicant's arguments filed 4/21/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “the modification is not supported by the combination; and would require "a difference in the structure disclosed by Kim", and therefore is not supported by the Examiner's assertions regarding the combination”. Remarks at pg. 11.
Examiner’s reply:
The examiner disagrees and relies upon new rationale and guidance from MPEP, and additional portions of the references as necessitated by the claim amendments which establish two functional groupings of terminals/electrodes.
Applicant argues:
Applicant argues with respect to amended claim 1 that “even under the broadest reasonable interpretation standard, the Office Action does not establish the cited art teaching or suggesting a plurality of terminals, including terminals (including terminals configured to provide at least one of the signal transmission, the power supply, or the grounding for the first semiconductor chip and terminals configured to not provide any of the signal transmission, the power supply, or the grounding for the first semiconductor chip) bonding the semiconductor chip 130 to another semiconductor chip”. Remarks at pg. 12.
Examiner’s reply:
The examiner disagrees and relies upon new rationale and guidance from MPEP, and additional portions of the references as necessitated by the claim amendments which establish two functional groupings of terminals/electrodes.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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