Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/2/2025 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: “wherein plurality of heat dispersion through electrodes” in line 23. For the sake of compact prosecution, claim 1 is interpreted in the instant Office action as follows: “wherein plurality of heat dispersion through electrodes” is found to be a typographical error and is believed to be equivalent to “the wherein plurality of heat dispersion through electrodes” based on antecedence for this term earlier in the claim; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20190206841 A1) in view of Seo (US 20160133613 A1).
Regarding claim 1, Kim discloses a semiconductor package (Fig. 1) comprising:
a wiring structure (100);
a semiconductor chip (200) on the wiring structure;
a plurality of internal terminals (a pair of 250) between the wiring structure and the semiconductor chip, each of the plurality of internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the semiconductor chip ([0072]: “electrically, connect”. Note: an electrical connection must necessarily include at least one of signal/power/ground);
a plurality of internal heat dispersion terminals (a different pair of 250) between the wiring structure and the semiconductor chip, each of the plurality of internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the semiconductor chip (250 is composed of matter and included between 100 and 200, therefore at least some amount of thermal conduction must occur through it. Accordingly, it must “disperse heat” to some extent.);
a high thermal conductivity layer (255. Note: This layer is composed of matter, and therefore it must necessarily have some amount of thermal conductivity greater than a vacuum, thus it has a “high thermal conductivity” relative to something. Additionally, Kim teaches 255 is configured as an underfill [0089]: “inter-chip molding material” which is consistent with Applicant’s disclosure [28] “may include an underfill”. Further, the claim as written reasonably includes materials with a wide range of thermal conductivity, thus the claimed “high” configuration does not establish a relation to any particular structure or range distinct from Kim: 255.) between the wiring structure and the semiconductor chip; and
an encapsulator (160) on the high thermal conductivity layer and contacting the semiconductor chip,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar (illustrated as exactly coplanar),
the wiring structure includes a plurality of through electrodes (a pair of 125 corresponding to the pair of 250) extending through the wiring structure and connected to the plurality of internal terminals (electrically connected is shown), and a plurality of heat dispersion through electrodes (a different pair of 125 corresponding to the different pair of 250, at least indirectly connected. Note: This pair of 125 is composed of matter, and therefore at least some amount of thermal conduction must occur through it. Accordingly, it must have “heat dispersion” relative to something.) extending through the wiring structure and electrically connected to at least a portion of the plurality of internal heat dispersion terminals (electrically connected is shown), […].
Illustrated below is a marked and annotated figure of Fig. 1 of Kim.
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Kim fails to teach “wherein plurality of heat dispersion through electrodes and the plurality of internal heat dispersion terminals, including the plurality of internal heat dispersion terminals electrically connected to the plurality of heat dispersion through electrodes are configured not to provide any of the signal transmission, the power supply, or the grounding for the semiconductor chip”.
Seo discloses through electrodes (Fig. 1: 135) and terminals (125) in the same field of endeavor; and further teaches these through electrodes and terminals may be configured as internal terminals and through electrodes ([0052]: “may be in a ground…state”); or alternatively heat dispersion through electrodes and internal heat dispersion terminals; wherein plurality of heat dispersion through electrodes and the plurality of internal heat dispersion terminals, including the plurality of internal heat dispersion terminals electrically connected to the plurality of heat dispersion through electrodes are configured not to provide any of the signal transmission, the power supply, or the grounding for the semiconductor chip ([0052]: “may be in a…floated state”).
Modifying the semiconductor package of Kim by including through electrodes and terminals having the functional configuration of Seo would arrive at the claimed terminal and through electrode configuration. Seo provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed configuration in that it would enhance heat dispersion, thereby providing enhanced functional characteristics of the package ([0052]: “allowing heat…to be dissipated”). A person of ordinary skill in the art before the effective filing date would have had predictable results because it is a difference in functional configuration that does not require a difference in the structure disclosed by Kim. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal and through electrode configuration because it would enhance functional characteristics of the package. MPEP 2143 (I)(G).
Regarding claim 2, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein an upper surface of the encapsulator (See annotated figure) includes a flat portion substantially parallel to the upper surface of the wiring structure (See annotated figure) and an inclined portion between the flat portion and the semiconductor chip (See annotated figure, showing a completely vertically inclined sidewall. Note: “between” is based on a Z height, without a Z direction overlap.).
Regarding claim 3, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the plurality of internal heat dispersion terminals extend through the high thermal conductivity layer (all 250 extend through at least a portion of 255 in the Z direction).
Regarding claim 5, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein each of the plurality of internal heat dispersion terminals includes the same material as the plurality of internal terminals (Kim singularly describes the collection of 250 in [0072] without any differing properties required; thus, the collection of 250 reasonably includes “the same material”).
Regarding claim 6, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the plurality of internal heat dispersion terminals are spaced apart from the plurality of internal terminals (spaced apart by intervening 255).
Regarding claim 7, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein each of the plurality of internal heat dispersion terminals has the same size as the plurality of internal terminals (Kim singularly describes the collection of 250 in [0072] without any differing properties required, thus the collection of 250 reasonably includes the same size).
Regarding claim 9, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein at least one of the plurality of internal heat dispersion terminals is not connected to either the plurality of through electrodes or the plurality of heat dispersion through electrodes (the particular combination of Seo disclosed by [0052]: “floated state”, included for the same reasons as reasoned in the claim 1 rejection, i.e., to enhance heat dispersion; [0052]: “allowing heat…to be dissipated”).
Regarding claim 10, Kim in view of Seo discloses a semiconductor package (Kim: Fig. 1), further comprising: a plurality of external terminals on a lower surface of the wiring structure and connected to the plurality of through electrodes (a pair of 150 corresponding to the pair of 150, electrically connected through intervening 117; [0038]: “electrically connected to the first TSVs”).
Regarding claim 11, Kim in view of Seo discloses the semiconductor package of claim 10 (Kim: Fig. 1), further comprising a plurality of external heat dispersion terminals on the lower surface of the wiring structure and connected to the plurality of heat dispersion through electrodes (a different pair of 150 corresponding to the different pair of 150, electrically connected through intervening 117; [0038]: “electrically connected to the first TSVs”).
Regarding claim 12, Kim in view of Seo discloses the semiconductor package of claim 11 (Kim: Fig. 1), wherein each of the plurality of external heat dispersion terminals includes the same material as the plurality of external terminals (Kim singularly describes the collection of 150 in [0117] without any differing properties required, thus the collection of 150 reasonably includes the same material).
Regarding claim 13, Kim in view of Seo discloses the semiconductor package of claim 11 (Kim: Fig. 1), wherein each of the plurality of external heat dispersion terminals has the same size as the plurality of external terminals (Kim singularly describes the collection of 150 in [0117] without any differing properties required, thus the collection of 150 reasonably includes the same size).
Regarding claim 14, Kim in view of Seo discloses the semiconductor package of claim 1 (Kim: Fig. 1), wherein the high thermal conductivity layer fills a space between the plurality of internal terminals and the plurality of internal heat dispersion terminals (255 is spatially intervening between the pair of 250 and the different pair of 250).
Regarding independent claim 15, Kim discloses a semiconductor package (Fig. 1) comprising:
a wiring structure (100);
a first semiconductor chip (200) on the wiring structure;
a plurality of first internal terminals (a pair of 250) between the wiring structure and the first semiconductor chip, each of the plurality of first internal terminals configured to provide at least one of a signal transmission, power supply, or grounding for the first semiconductor chip ([0072]: “electrically, connect”. Note: an electrical connection must necessarily include at least one of signal/power/ground);
a plurality of first internal heat dispersion terminals (a different pair of 250) between the wiring structure and the first semiconductor chip, each of the plurality of first internal heat dispersion terminals configured to disperse heat generated by the wiring structure and the first semiconductor chip (250 is composed of matter and included between 100 and 200, therefore at least some amount of thermal conduction must occur through it. Accordingly, it must “disperse heat” to some extent.) […];
a second semiconductor chip (300) on the first semiconductor chip;
a plurality of second internal terminals (a pair of 350) between the first semiconductor chip and the second semiconductor chip,
a first high thermal conductivity layer (255. Note: This layer is composed of matter, and therefore it must necessarily have some amount of thermal conductivity greater than a vacuum, thus it has a “high thermal conductivity” relative to something. Additionally, Kim teaches 255 is configured as an underfill [0089]: “inter-chip molding material” which is consistent with Applicant’s disclosure [28] “may include an underfill”. Further, the claim as written reasonably includes materials with a wide range of thermal conductivity, thus the claimed “high” configuration does not establish a relation to any particular structure or range distinct from Kim: 255.) between the wiring structure and the first semiconductor chip; and
an encapsulator (160) on the first high thermal conductivity layer,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar (illustrated as exactly coplanar) and
wherein the first high thermal conductivity layer covers an upper surface of the wiring structure (255 directly covers some of 100) and side surfaces of the first semiconductor chip (255 bulges beyond 200, thus it meets and covers the edge of the side surfaces, and indirectly covers additional portions of the side surfaces),
the wiring structure includes a plurality of first through electrodes (a pair of 125 corresponding to the pair of 250) extending through the wiring structure and connected to the plurality of first internal terminals (electrically connected is shown), and a plurality of first heat dispersion through electrodes (a different pair of 125 corresponding to the different pair of 250, at least indirectly connected. Note: This pair of 125 is composed of matter, and therefore at least some amount of thermal conduction must occur through it. Accordingly, it must have “heat dispersion” relative to something.) extending through the wiring structure and electrically connected to at least a portion of the plurality of first internal heat dispersion terminals (electrically connected is shown), […].
Kim fails to teach “each of the plurality of first internal heat dispersion terminals configured […] not to provide at least one of the signal transmission, the power supply, or the grounding for the first semiconductor chip; […]
the plurality of first heat dispersion through electrodes and the plurality of first internal heat dispersion terminals, including the plurality of first internal heat dispersion terminals connected to the plurality of first heat dispersion through electrodes, are configured not to provide the signal transmission, the power supply, or the grounding for the first semiconductor chip”.
Seo discloses through electrodes (Fig. 1: 135) and terminals (125) in the same field of endeavor; and further teaches these through electrodes and terminals may be configured as first internal terminals and first through electrodes ([0052]: “may be in a ground…state”); or alternatively first heat dispersion through electrodes and first internal heat dispersion terminals; wherein each of the plurality of first internal heat dispersion terminals configured […] not to provide at least one of the signal transmission, the power supply, or the grounding […] the plurality of first heat dispersion through electrodes and the plurality of first internal heat dispersion terminals, including the plurality of first internal heat dispersion terminals connected to the plurality of first heat dispersion through electrodes, are configured not to provide the signal transmission, the power supply, or the grounding for the first semiconductor chip ([0052]: “may be in a…floated state”).
Modifying the semiconductor package of Kim by including through electrodes and terminals having the functional configuration of Seo would arrive at the claimed terminal and through electrode configuration. Seo provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed configuration in that it would enhance heat dispersion, thereby providing enhanced functional characteristics of the package ([0052]: “allowing heat…to be dissipated”). A person of ordinary skill in the art before the effective filing date would have had predictable results because it is a difference in functional configuration that does not require a difference in the structure disclosed by Kim. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal and through electrode configuration because it would enhance functional characteristics of the package. MPEP 2143 (I)(G).
Regarding claim 16, Kim in view of Seo discloses the semiconductor package of claim 15 (Kim: Fig. 1), wherein the first semiconductor chip includes a plurality of second through electrodes extending through the first semiconductor chip and connected to the plurality of first internal terminals (a pair of 225 corresponding to the pair of 250, at least physically connected through intervening 217).
Regarding claim 17, Kim in view of Seo discloses the semiconductor package of claim 16 (Kim: Fig. 1), wherein the plurality of second internal terminals are connected to the plurality of second through electrodes (illustrated as connected).
Regarding claim 18, Kim in view of Seo discloses the semiconductor package of claim 16 (Kim: Fig. 1), wherein at least one of the plurality of first internal heat dispersion terminals is not connected to either the plurality of first through electrodes or the plurality of first heat dispersion through electrodes (the particular combination of Seo disclosed by [0052]: “floated state”, included for the same reasons as reasoned in the claim 1 rejection, i.e., to enhance heat dispersion; [0052]: “allowing heat…to be dissipated”), wherein the first semiconductor chip includes a plurality of second heat dispersion through electrodes extending through the first semiconductor chip and connected to the plurality of first internal heat dispersion terminals (a different pair of 225 corresponding to the different pair of 250, at least physically connected through intervening 217).
Regarding claim 19, Kim in view of Seo discloses the semiconductor package of claim 18 (Kim: Fig. 1), further comprising a plurality of second internal heat dispersion terminals between the first semiconductor chip and the second semiconductor chip (a different pair of 350), wherein the plurality of second internal heat dispersion terminals are connected to the plurality of second heat dispersion through electrodes and spaced apart from the plurality of second internal terminals (illustrated as connected, spaced apart by intervening 355).
Regarding claim 20, Kim in view of Seo discloses the semiconductor package of claim 15 (Kim: Fig. 1), further comprising a second high thermal conductivity layer between the first semiconductor chip and the second semiconductor chip (355), wherein the first semiconductor chip is surrounded by the first high thermal conductivity layer and the second high thermal conductivity layer (at least partially surrounding the upper and lower surfaces of 200), and wherein the encapsulator is on the second high thermal conductivity layer (160 is directly on 355) and spaced apart from the first semiconductor chip (at least a portion of 160 is spaced apart from a portion of 200 by intervening 255).
Response to Arguments
Applicant's arguments filed 12/2/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 15 that “the cited art fails to disclose or suggest all the elements recited by claims 1 and 15”. Remarks at pg. 8.
Examiner’s reply:
The examiner agrees for reasons consistent with Applicants remarks here and in prior entries to the record. However, the examiner notes a new reference (Seo) is relied upon for the instant Office action as necessitated by claim amendment. Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817