Prosecution Insights
Last updated: August 14, 2026
Application No. 18/593,387

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Mar 01, 2024
Priority
Jun 15, 2018 — JP 2018-114345 +3 more
Examiner
FARMER, EMILY NICOLE
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
39 granted / 44 resolved
+20.6% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
12 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
58.9%
+18.9% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
11.0%
-29.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 44 resolved cases

Office Action

§102 §103
CTNF 18/593,387 CTNF 99851 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-4 are pending. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to JP2018-114345 for 06/15/2018. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/01/2024 has been considered by the examiner. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: HETEROJUNCTION BIPOLAR TRANSISTOR HAVING AN OCTAGONAL EMITTER ELECTRODE OHMIC CONTACT INTERFACE AND CONTACT HOLE Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim 1 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Min et al. (US PGPub 2006/0099767; herein known as Min) . Regarding claim 1 , Min teaches (Fig. 1E) a semiconductor device comprising: a collector layer (120, [0029]), a base layer (130, [0029]) and an emitter layer (140, 150, [0029]) that are disposed on a substrate (100, [0029]) to form a bipolar transistor ([0029]); and an emitter electrode (160, [0030]) that is in ohmic contact with the emitter layer (140 and 150 are formed of InP and InGaAs, respectively, and the emitter electrode is formed of a metal, which necessarily form an ohmic contact at their interface. Additionally, the specification of the instant application teaches wherein the top layer of the emitter layer is formed of InGaAs and the emitter electrode is a metal, and wherein that interface forms an ohmic contact, therefore as Min teaches the same materials, the resulting interface will inherently have the same properties, i.e. an ohmic contact), wherein the emitter layer has a shape that is long in one direction (011) in plan view, and an ohmic contact interface (interface between 160 and 150) at which the emitter layer and the emitter electrode are in ohmic contact with each other has a planar shape in which at least one corner of a rectangle is chamfered ([0037]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kusano et al. (JP 2005/101402; herein known as Kusano, English translation cited and provided for reference) . Regarding claim 3, Kusano teaches a semiconductor device comprising: a collector layer (13, [0023]), a base layer (14, [0023]) and an emitter layer (15, 16, [0026]) that are disposed on a substrate (11, [0023]) to form a bipolar transistor ([0001]); and an emitter electrode (17, [0025]) that is in ohmic contact with the emitter layer ([0024]); and an emitter wiring line (M1e, [0036]) connected to the emitter electrode through a contact hole (21e, [0034]) formed in an insulating film (20a, [0034]), wherein the emitter layer has a shape that is long in one direction in plan view (x-direction). Kusano does not explicitly teach wherein the contact hole has a planar shape in which at least one corner of a rectangle is chamfered. Kusano does teach wherein the contact hole shape is determined to match the shape of the emitter electrode ([0041]), and wherein shape and size of the contact hole effects distribution of temperature across the emitter to reduce concentration of heat generation ([0042]) as a result-effective variable of the area of the contact hole. Absent a teaching of criticality in the specification of the claimed chamfered rectangle by the instant application, evidenced by teaching of multiple contact hole shapes, with no discussion of the effect of the change of shape, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the contact hole has a planar shape in which at least one corner of a rectangle is chamfered in order to modify distribution of temperature across the emitter to reduce concentration of heat generation. See MPEP 2144.05(II)(b) . Allowable Subject Matter 07-43 Claims 2 and 4 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the respective base claim and any intervening claims. Regarding claim 2, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the semiconductor device of claim 1 wherein a distance from an end portion of the emitter layer in a longitudinal direction to a farthest position of a chamfered portion of the ohmic contact interface with respect to the longitudinal direction of the emitter layer is 3 μm or more. Min teaches wherein a distance from the end portion of the emitter to the ohmic contact interface is a result effective variable of the angle of the chamfer of the ohmic contact interface, but the instant application teaches criticality of 3 μm or more for the express purpose of increasing the transition voltage of the device, shown in Fig. 8 and described in paragraphs 0082-0083. Thus, as the claimed feature is critical, and Min does not provide a specific reason to use that specific parameter of 3um, a prima facie case of obviousness cannot be established. Therefore, the prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed. Regarding claim 4, the cited prior art of record does not teach nor fairly suggest, along with the other claimed features, the semiconductor device of claim 3, wherein a distance from an end portion of the emitter layer in a longitudinal direction to a farthest position of a chamfered portion of the contact hole with respect to the longitudinal direction of the emitter layer is 4 μm or more. Kusano teaches a contact hole that is an unspecified distance away from an end portion of an emitter layer. While Kusano does teach that a contact hole can be placed in order to affect the thermal stresses of the device, it does not further specify nor suggest a distance or range of distances from the end of the emitter layer. Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : KR20060007677A – Ki US Patent 7829917 – Thomas US PGPub 20150380401 – Ishii et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY FARMER/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/593,387 Page 2 Art Unit: 2812 Application/Control Number: 18/593,387 Page 3 Art Unit: 2812 Application/Control Number: 18/593,387 Page 4 Art Unit: 2812 Application/Control Number: 18/593,387 Page 5 Art Unit: 2812 Application/Control Number: 18/593,387 Page 6 Art Unit: 2812 Application/Control Number: 18/593,387 Page 7 Art Unit: 2812
Read full office action

Prosecution Timeline

Mar 01, 2024
Application Filed
May 05, 2026
Non-Final Rejection mailed — §102, §103
Aug 03, 2026
Examiner Interview Summary
Aug 03, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707879
DISPLAY DEVICE
2y 10m to grant Granted Aug 11, 2026
Patent 12684901
OPTOELECTRONIC DEVICE AND METHOD FOR PROCESSING THE SAME
2y 7m to grant Granted Jul 14, 2026
Patent 12672564
TECHNOLOGIES FOR VERTICALLY INTERCONNECTED GLASS CORE ARCHITECTURE
3y 6m to grant Granted Jun 30, 2026
Patent 12652843
HIGH BAND-GAP DEVICES WITH A DOPED HIGH BAND-GAP GATE ELECTRODE EXTENSION
3y 10m to grant Granted Jun 09, 2026
Patent 12635419
STACKED SPIN-ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY
4y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
96%
With Interview (+7.1%)
3y 1m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 44 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month