Prosecution Insights
Last updated: July 17, 2026
Application No. 18/593,388

STACKED FET WITH STACKED POWER RAIL

Non-Final OA §103
Filed
Mar 01, 2024
Examiner
LIU, XIAOMING
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
514 granted / 596 resolved
+18.2% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
36 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
89.3%
+49.3% vs TC avg
§102
6.1%
-33.9% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 596 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/1/2024 and 4/30/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2022/0216340 in view of Dewey et al. US 2023/0197569. Re claim 1, Lin teaches a semiconductor device (200, fig20, [13]), comprising: a stacked transistor structure having field effect transistors on at least two levels (204B and 204T, fig5 and 20, [16]), the at least two levels including a top side (204T, fig9 and 20, [16]) and bottom side (204B, fig7 and 20, [16]); a bottom power rail (286, fig20, [38]) disposed on the bottom side on source/drain regions (228-1, fig20, [38]) of the field effect transistors; and a top power rail (276, fig20, [37]) disposed on the top side on source/drain regions (248-1, fig20, [37]) of the field effect transistors. Lin does not explicitly show a bottom power rail disposed on the bottom side between source/drain regions of the field effect transistors; and a top power rail disposed on the top side between source/drain regions of the field effect transistors. Dewey teaches forming U shaped S/D contacts (236, fig2H, [50]) in S/D region. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Dewey to form U shaped top and bottom power rail in region 228-1 and 248-1 of Lin with isolation layer 242 of Lin formed between the two power rails. The motivation to do so is to increase contact area between the power rail and the S/D region and create a more robust ohmic contact with lower contact resistance (Dewey, [9]). Re claim 2, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail and the top power rail are vertically disposed relative to one another (Lin, U shaped 276 formed in 248-1 and U shaped 286 in 228-1, fig20). Re claim 3, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) are separated by a power rail barrier (Lin, 242, fig10, 20, [25]). Re claim 4, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail connects to a bottom source/drain region (Lin, U shaped 286 in 228-1, fig20). Re claim 5, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the top power rail connects to a top source/drain region (Lin, U shaped 276 formed in 248-1, fig20). Re claim 6, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) together provide positive and negative supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 7, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) provide positive supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 8, Lin modified above teaches the semiconductor device as recited in claim 1, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) provide negative supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 9, Lin teaches a semiconductor device (200, fig20, [13]), comprising: a stacked transistor structure having field effect transistors on at least two levels (204B and 204T, fig5 and 20, [16]), the at least two levels including a top side (204T, fig9 and 20, [16]) and bottom side (204B, fig7 and 20, [16]); and a stacked power rail (276,286, fig20, [37, 38]) disposed between the field effect transistors on the at least two levels, Lin does not explicitly show the stacked power rail having: a bottom power rail electrically isolated from surrounding structures by a first dielectric spacer; and a top power rail electrically isolated from surrounding structures by a second dielectric spacer. Dewey teaches bottom power rail (246, fig2L, [56]) electrically isolated from surrounding structures by a first dielectric spacer (242, fig2L, [56]); and a top power rail (236, fig2H, [49]) electrically isolated from surrounding structures by a second dielectric spacer (234, fig2H, [49]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Dewey to form U shaped top and bottom power rail with dielectric spacers in region 228-1 and 248-1 of Lin and isolation layer 242 of Lin formed between the two power rails. The motivation to do so is to increase contact area between the power rail and the S/D region and create a more robust ohmic contact with lower contact resistance (Dewey, [9]). Re claim 10, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) are separated by a power rail barrier (Lin, 242, fig10, 20, [25]). Re claim 11, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the bottom power rail connects to a bottom source/drain region (Lin, U shaped 286 in 228-1, fig20). Re claim 12, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the top power rail connects to a top source/drain region (Lin, U shaped 276 formed in 248-1, fig20). Re claim 13, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) together provide positive and negative supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 14, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) provide positive supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 15, Lin modified above teaches the semiconductor device as recited in claim 9, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) provide negative supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Claim(s) 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2022/0216340 in view of Dewey et al. US 2023/0197569 and Peng et al. US 2022/0123023. Re claim 16, Lin teaches a semiconductor device (200, fig20, [13]), comprising: a stacked transistor structure having field effect transistors on at least two levels (204B and 204T, fig5 and 20, [16]), the at least two levels including a top side (204T, fig9 and 20, [16]) and bottom side (204B, fig7 and 20, [16]); and a stacked power rail (276, 286, fig20, [37, 38]) disposed between the field effect transistors on the at least two levels, a power rail barrier (242, fig10, 20, [25]) electrically separating the top power rail (276, fig20, [37, 38]) from the bottom power rail (286, fig20, [37, 38]). Lin does not explicitly show the stacked power rail having: a bottom power rail electrically isolated from the field effect transistors and gates by a first dielectric spacer, the bottom power rail being connected to a backside power rail; a top power rail electrically isolated from the field effect transistors and gates by a second dielectric spacer, the top power rail being connected to a frontside component; and a power rail barrier connecting the first dielectric spacer and the second dielectric spacer and electrically separating the top power rail from the bottom power rail. Dewey teaches a bottom power rail (246, fig2L, [56]) electrically isolated from the field effect transistors and gates by a first dielectric spacer (242 and part of 212 along 246, fig2L, [44, 56]); a top power rail (236, fig2H, [49]) electrically isolated from the field effect transistors and gates by a second dielectric spacer (234 and part of 212 along 236, fig2H, [44, 49]); and a power rail barrier (232, fig2G, [48]) connecting the first dielectric spacer (242 and top part of 212, fig2L, [44, 56]) and the second dielectric spacer (234 and bottom part of 212, fig2H, [44, 49]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Dewey to form U shaped top and bottom power rail with dielectric spacers in region 228-1 and 248-1 of Lin with isolation layer 242 of Lin formed between the two power rails. The motivation to do so is to increase contact area between the power rail and the S/D region and create a more robust ohmic contact with lower contact resistance (Dewey, [9]). Peng teaches the bottom power rail (556 connected with S/D 113/114, fig5D, [45, 86]) being connected to a backside power rail (132, fig5D, [56]); the top power rail (556 connected with S/D 123/124, fig5D, [49, 86]) being connected to a frontside component (142, fig5D, [57). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin in view of Dewey and Peng to connect the U shaped top and bottom power rail with frontside power rail 142 VDD and backside power rail 132 VSS. The motivation to do so is to effectively decrease the resistance and power consumption of the device by forming power rails with adequate line width while decreasing the distance of the conduction path (Peng, [41]). Re claim 17, Lin modified above teaches the semiconductor device as recited in claim 16, wherein the bottom power rail connects to a bottom source/drain region (Lin, U shaped 286 in 228-1, fig20). Re claim 18, Lin modified above teaches the semiconductor device as recited in claim 16, wherein the top power rail connects to a top source/drain region (Lin, U shaped 276 formed in 248-1, fig20). Re claim 19, Lin modified above teaches the semiconductor device as recited in claim 16, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) together provide positive and negative supply voltages ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey and Peng teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Re claim 20, Lin modified above teaches the semiconductor device as recited in claim 16, wherein the bottom power rail (Lin, U shaped 286 in 228-1, fig20) and the top power rail (Lin, U shaped 276 formed in 248-1, fig20) provide a same supply voltage ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Lin in view of Dewey and Peng teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 01, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12660230
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME
3y 7m to grant Granted Jun 16, 2026
Patent 12660307
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
3y 3m to grant Granted Jun 16, 2026
Patent 12641872
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
3y 2m to grant Granted May 26, 2026
Patent 12635508
INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND A METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted May 19, 2026
Patent 12633457
CAPACITOR, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR, AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR DEVICE
2y 10m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+10.9%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 596 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month