DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 07/20/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-15, in the reply filed on 07/20/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/01/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-10 and 11-15 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite. Claim 8 recites “a plurality of second pillars … having a pitch narrower than a maximum value of a cross-sectional area in the first contact.” The claim compares a “pitch” (a one-dimensional spacing, having units of length) to a “cross-sectional area” (a two-dimensional quantity, having units of length squared). Because a length cannot be meaningfully compared as “narrower than” an area, the metric by which the pitch and the cross-sectional area are to be compared is indeterminate, and the scope of the limitation cannot be ascertained. Clarification is required (e.g., comparison to a maximum cross-sectional dimension/diameter of the first contact).
Claim 11 is rejected under 35 U.S.C. 112(b) as being indefinite. Claim 11 recites an insulating layer “near a center of the stacked body in the stacking direction.” The term “near” is a term of degree, and the claim does not provide a standard for ascertaining how close to the center the insulating layer must be located. See MPEP 2173.05(b). While claim 13 later recites that the insulating layer has the largest thickness, claim 11 standing alone lacks a comparable standard, rendering its scope unclear. Clarification is required.
Claims 9-10 and 12-15 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2021/0296239 A1 (Yoshimizu).
Regarding claim 1, Yoshimizu discloses, a semiconductor storage device comprising: “a first stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in a stacking direction,” which is Yoshimizu’s lower memory cell array layer LMCA2 having conductive layers alternating with insulating layers, (LMCA2/110/101; lower memory cell array layer with conductive layers 110 and insulating layers 101; Yoshimizu Fig. 4; [0052]–[0053]);
“a second stacked body that is disposed above the first stacked body and in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked in the stacking direction,” which is Yoshimizu’s upper memory cell array layer LMCA1 (upper/lower being relative terms; Yoshimizu being a wafer-bonded/inverted array, see MPEP 2144.04(VI)), (LMCA1/110/101; upper memory cell array layer; Yoshimizu Fig. 4; [0052]);
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“a first pillar that extends in the first and second stacked bodies in the stacking direction and has a semiconductor layer and a memory layer that covers a side wall of the semiconductor layer,” which is Yoshimizu’s memory pillar having a semiconductor (channel) layer 120 and a gate insulating film 130 (tunnel 131 / charge storage 132 / block 133) covering the side wall, (120/130; semiconductor layer and gate insulating/memory film; Yoshimizu Fig. 9; [0049]);
“a first contact that extends in the first and second stacked bodies in the stacking direction and is connected to one first conductive layer of the plurality of first conductive layers,” which is Yoshimizu’s contact 161, an upper surface of which is in contact with a lower surface of one conductive layer 110, (161; contact; Yoshimizu Fig. 10; [0054]);
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“wherein the first contact has a first portion that extends in the first stacked body and is connected at a lower end portion thereof to the one first conductive layer,” which is the wider (“flower-like”) portion of contact 161 in lower array LMCA2 that connects to the one conductive layer 110, (161 in LMCA2; wider lower portion of the contact; Yoshimizu Fig. 11; [0054]);
“a second portion that extends in the second stacked body and is connected to an upper end portion of the first portion, the second portion having a cross-sectional area at a lower end portion thereof as viewed from the stacking direction that is smaller than a cross-sectional area at the upper end portion of the first portion as viewed from the stacking direction,” which is the narrower portion of contact 161 in upper array LMCA1, the cross-section of contact 161 discontinuously changing at boundary insulating layer 115 such that it is smaller above than below, (161 in LMCA1 / 115; narrower upper portion and boundary insulating layer; Yoshimizu Fig. 10; [0055]);
“a third conductive layer that continuously extends in the first and second portions in the stacking direction,” which is the single conductive body of contact 161 continuously filling both the wider lower and narrower upper portions, (161; continuous conductive contact body; Yoshimizu Fig. 10; [0054] – [0055]);
Regarding claim 2, Yoshimizu teaches, “the semiconductor storage device according to claim 1, wherein the first and second portions are connected to each other in an uppermost first insulating layer among the plurality of first insulating layers of the first stacked body,” in that the wider lower portion and narrower upper portion of contact 161 join at insulating layer 115 located at the boundary at the top of lower array LMCA2, (115; boundary insulating layer atop LMCA2; Yoshimizu Fig. 10; [0055]);
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Regarding claim 3, Yoshimizu teaches, “the semiconductor storage device according to claim 2, wherein the upper end portion of the first portion is located in the uppermost first insulating layer and the lower end portion of the second portion is located in the uppermost first insulating layer,” in that both the top of the wider portion and the bottom of the narrower portion of contact 161 lie in boundary insulating layer 115, (115; boundary insulating layer; Yoshimizu Fig. 10; [0103]);
Claim 11 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2021/0296239 A1 (Yoshimizu).
Regarding claim 11, Yoshimizu teaches, a semiconductor storage device comprising:
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“a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked in a stacking direction,” which is Yoshimizu’s stacked memory cell array (LMCA1 and LMCA2) of conductive layers 110 and insulating layers 101, (110/101; conductive layers and insulating layers; Yoshimizu Fig. 4; [0052]–[0053]);
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“a pillar that extends in the stacked body in a stacking direction of the stacked body and has a semiconductor layer and a memory layer that covers a side wall of the semiconductor layer,” which is Yoshimizu’s memory pillar (semiconductor layer 120 and gate insulating/memory film 130), (120/130; semiconductor layer and gate insulating/memory film; Yoshimizu Fig. 9; [0049]);
“a conductive contact that extends in the stacked body in the stacking direction and is connected to one of the plurality of conductive layers,” which is Yoshimizu’s contact 161 in contact with one conductive layer 110, (161; conductive contact; Yoshimizu Fig. 10; [0054]);
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“wherein the conductive contact has a central portion that is in an insulating layer, which is one of the plurality of insulating layers near a center of the stacked body in the stacking direction, in which a cross-sectional area thereof as viewed from the stacking direction is discontinuously changed,” which is the portion of contact 161 at boundary insulating layer 115 located near the center of the stack (between LMCA1 and LMCA2), where the cross-section discontinuously changes, (115; central/boundary insulating layer; Yoshimizu Fig. 10; [0054]);
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“the cross-sectional area of the central portion is smaller on an upper surface side of the insulating layer than on a lower surface side of the insulating layer,” in that contact 161 is narrower in the upper array LMCA1 than the wider “flower-like” portion in the lower array LMCA2, (161; narrower-upper / wider-lower contact; Yoshimizu Fig. 11; [0054]);
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296239 A1 (Yoshimizu) and further in view of US 2020/0286828 A1 (Hosotani).
Regarding claim 4, Yoshimizu teaches the contact of claim 1 having first and second portions as set forth above, but does not expressly teach a third portion narrower than the second;
However, in analogous art, Hosotani teaches, “wherein the first contact further has a third portion that is connected to an upper end portion of the second portion, the third portion having a cross-sectional area at a lower end portion thereof as viewed from the stacking direction that is smaller than a cross-sectional area at the upper end portion of the second portion as viewed from the stacking direction,” in that Hosotani teaches a multi-tier contact passing through plural tier boundaries — contact plug CBL_2 formed on contact plug CH_1 across the inter-tier insulating layer 52 — providing successive stepped portions, each upper portion being narrower than the portion below it, (CBL_2/CH_1/52; multi-tier stepped contact portions across the inter-tier insulating layer; Hosotani Fig. 20; [0198] – [0205]);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu and Hosotani before him/her, to have a third portion of the conyact, (1) because providing an additional stepped (third) contact portion permits the contact to reach word lines through additional stacked tiers while confining the etch profile and reducing damage to adjacent structures; (2) since the modification amounts to a simple duplication/rearrangement of the known stepped contact portions of Hosotani (MPEP 2144.04); and (3) with a reasonable expectation of success, yielding the predictable result of a reliable deep word-line connection. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Hosotani while forming a stacked word-line contact of Yoshimizu.
Regarding claim 5, the combination of Yoshimizu and Hosotani teaches the following limitation, where Yoshimizu teaches the first and second portions and Hosotani teaches the continuity of the conductor through the additional stepped portion: “the semiconductor storage device according to claim 4, wherein the third conductive layer continuously extends in the first, second, and third portions in the stacking direction,” in that Hosotani’s multi-tier contact remains a single continuous conductive body across the successive stepped portions, (40; continuous contact conductor across tiers; Hosotani Fig. 14; [0150] – [0152]);
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296239 A1 (Yoshimizu) and further in view of US 2022/0045095 A1 (Watanabe1).
Regarding claim 6, Yoshimizu teaches the device of claim 4, but does not expressly teach, a separate second contact extending in the second (upper) stacked body only;
However, in analogous art, Watanabe1 teaches the following limitations:
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“a second contact that extends in the second stacked body in the stacking direction and is connected to one second conductive layer of the plurality of second conductive layers,” in that Watanabe1 teaches a contact CC connected to a word line WL of the upper stacked structure LMb only (FIG. 3B), separate from through-stack contacts, (CC; upper-stack-only contact to word line WL of LMb; Watanabe1 Fig. 3B; [0053])
“wherein the second contact has a fourth portion that extends in the second stacked body and is connected at a lower end portion thereof to the one second conductive layer, a fifth portion that is connected to an upper end portion of the fourth portion, the fifth portion having a cross-sectional area at a lower end portion thereof as viewed from the stacking direction that is smaller than a cross-sectional area at the upper end portion of the fourth portion, a fourth conductive layer that continuously extends in the fourth and fifth portions in the stacking direction,” in that Watanabe1’s contacts CC are formed by progressive etching of contact holes to different depths (a lower/wider portion and an upper/narrower portion joined stepwise), lined by insulating layer 55 and continuously filled with a single tungsten conductor, (CC/55; stepped upper-stack contact with insulating liner and continuous tungsten fill; Watanabe1 Fig. 3C; [0097]);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu and Watanabe1 before him/her, to form a second contact because (1) providing a separate second contact that reaches an upper-stack word line independently leads out the upper-deck word lines of a multi-deck array; (2) since the modification amounts to a simple substitution/duplication of one known contact for another of Watanabe1 (MPEP 2144.04/2144.06); and (3) with a reasonable expectation of success, yielding the predictable result of selectively contacting each deck’s word lines with the same conductive fill. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Watanabe1 while forming a stacked word-line contact structure of Yoshimizu.
Regarding claim 7, the combination of Yoshimizu and Watanabe1 teaches the following limitation, where Yoshimizu teaches the third conductive layer (contact 161) and Watanabe1 teaches the fourth conductive layer (contact CC), both of the same material: “wherein the third conductive layer and the fourth conductive layer are made of the same conductive material,” in that both Yoshimizu’s contact 161 (tungsten; [0053]; Yoshimizu) and Watanabe1’s contact CC are filled with the same conductive material (e.g., tungsten), (CC; tungsten contact fill; Watanabe1 Fig. 3C; [0044])
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0296239 A1 (Yoshimizu) and further in view of US 2022/0084910 A1 (Karyu).
Regarding claim 8 (examined as best understood, see the §112(b) rejection above), Yoshimizu teaches the device of claim 6 and support structures 153, but does not expressly teach the second (support) pillars arranged in the contact region separate from the memory-pillar region;
However, in analogous art, Karyu teaches the following limitation, “a plurality of second pillars that extend in the first and second stacked bodies in the stacking direction … wherein the second pillars are arranged in a region where the first and second contacts are arranged, and the first pillar and a plurality of third pillars having the same structure as the first pillar are arranged in a region different from where the first and second contacts and the second pillars are arranged,” in that Karyu teaches columnar portions HR arranged in a matrix in the through contact region TPc (support pillars in the contact region), while memory pillars PL are arranged in the separate memory region MR, (HR; columnar support pillars in through contact region TPc; Karyu Fig. 2C; [0073]–[0074]); (PLa/PLb; memory pillars in memory region MR; Karyu Fig. 2A; [0053] - [0054]);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu and Karyu before him/her, and form the second (support) pillars arranged in the contact region separate from the memory-pillar region, (1) because arranging support columnar portions in the contact region stabilizes the stacked structure during replacement (word-line) processing and tolerates contact overlap; (2) since the modification amounts to a simple arrangement/duplication of known support parts of Karyu (MPEP 2144.04); and (3) with a reasonable expectation of success, yielding the predictable result of a mechanically stable stack whose contacts may overlap the support pillars. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Karyu while forming the contact region of Yoshimizu.
Regarding claim 9, the combination of Yoshimizu and Karyu teaches the following limitation, where Yoshimizu teaches the overlap of the contact and the support pillar and Karyu teaches the support (second) pillars in the contact region: “wherein at least one of the first and second contacts is disposed at a position overlapping one of the second pillars when viewed from the stacking direction,” in that Yoshimizu expressly teaches contact 161 provided at a location overlapping several support structures 153 when viewed from the stacking direction, (153; support structures overlapped by the contact; Yoshimizu Fig. 4; [0052]);
Regarding claim 10, the combination of Yoshimizu and Karyu teaches the following limitation: “wherein the first pillar and the third pillars are arranged at a higher density than the second pillars,” in that Karyu’s memory pillars PL populate the memory region MR as the dense operative array, whereas the support columnar portions HR are more sparsely distributed in the contact region — a higher memory-pillar density being an obvious arrangement of parts (MPEP 2144.04), (PLa/PLb vs. HR; higher-density memory pillars vs. sparser support pillars; Karyu Fig. 1B/2C; [0053] - [0054], [0073]–[0074]);
Claim 12 is rejected under under 35 U.S.C. 103 as unpatentable over US 2021/0296239 A1 (Yoshimizu) and further in view of US 2020/0286828 A1 (Hosotani).
Regarding claim 12, Yoshimizu teaches the device of claim 11, but does not expressly teach a neck portion at the upper end of the contact;
However, in analogous art, Hosotani teaches the following limitation: “wherein the conductive contact further has a neck portion at an upper end thereof, the neck portion having a cross-sectional area as viewed from the stacking direction that is smaller than a cross-sectional area at an upper portion of the conductive contact that is below the neck portion,” in that Hosotani’s multi-tier contact presents a narrowed upper (coupling/neck) region above a wider lower portion of the contact, (57; narrowed upper coupling/neck portion; Hosotani Fig. 14; [0152]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu and Hosotani before him/her, and form a a neck portion at the upper end of the contact, (1) because a narrowed upper neck focuses and shields the etch during hole-bottom processing, reducing damage to adjacent structures; (2) since the modification amounts to a mere change in shape/size of a known contact of Hosotani (MPEP 2144.04); and (3) with a reasonable expectation of success, yielding the predictable result of reduced etch damage to structures adjacent the contact. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Hosotani while forming the conductive contact of Yoshimizu.
Claims 13-14 are rejected under under 35 U.S.C. 103 as unpatentable over Yoshimizu in view of Hosotani and further in view of US 2022/0084910 A1 (Karyu).
Regarding claim 13, the combination of Yoshimizu and Hosotani fails to teach explicitly, the semiconductor storage device according to claim 12, wherein the insulating layer has the largest thickness among the insulating layers stacked in the stacked body.
However, in analogous art, Karyu teaches: “wherein the insulating layer has the largest thickness among the insulating layers stacked in the stacked body,” in that the inter-deck/boundary insulating layer (Yoshimizu’s layer 115; Karyu’s junction layer JL) is a distinct bonding/etch-stop layer between the two stacks, and making that inter-deck insulating layer the thickest of the insulating layers is an obvious change in size/proportion to accommodate the seam and landing tolerance (MPEP 2144.04 (IV)), (JL; inter-deck junction insulating layer; Karyu Fig. 2C; [0039]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu, Hosotani and Karyu before him/her, and use the insulating layer having the largest thickness among the insulating layers stacked in the stacked body, (1) because a thickest inter-deck insulating layer provides a robust seam/etch-stop, and support pillars arranged at lower density in the contact region mechanically support the stack while the contact overlaps/contacts them; (2) since the modification amounts to an obvious change in size and arrangement of known parts of Hosotani and Karyu (MPEP 2144.04); and (3) with a reasonable expectation of success, yielding the predictable result of a reliable, well-supported deep contact. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Hosotani and Karyu while forming the contact region of Yoshimizu.
Regarding claim 14, the combination of Yoshimizu, Hosotani and Karyu teaches, where Karyu teaches the first/second regions and their relative densities and Yoshimizu teaches the contact in contact with a support (second) pillar: “a plurality of first pillars arranged in a first region at a first density … and a plurality of second pillars arranged in a second region at a second density that is lower than the first density … wherein the conductive contact is also arranged in the second region and is in contact with one of the second pillars,” in that Karyu teaches memory pillars PL in the dense memory region MR (first region/first density) and support columnar portions HR in the through contact region TPc (second region/second, lower density), and Yoshimizu teaches contact 161 overlapping/contacting support structures 153, (PL/HR; higher-density memory region and lower-density support-pillar contact region; Karyu Fig. 2A/2C; [0053] - [0054], [0073]–[0074]); (153; support structure contacted by contact 161; Yoshimizu Fig. 4; [0052]).
Claim 15 is rejected under 35 U.S.C. 103 as unpatentable over Yoshimizu and further in view of US 2022/0084910 A1 (Karyu).
Regarding claim 15, Yoshimizu teaches the device of claim 11 but fails to teach explicitly, an insulating layer that electrically isolates the conductive contact from the conductive layers in the stacked body except for the one conductive layer that the conductive contact is connected to.
However, in analogous art, Karyu teaches the following limitation: “an insulating layer that electrically isolates the conductive contact from the conductive layers in the stacked body except for the one conductive layer that the conductive contact is connected to,” in that Karyu teaches an insulating layer 55 that covers the side wall of contact C4, thereby isolating the contact from the conductive layers it passes and leaving only the target conductive layer connected, (55; sidewall insulating layer isolating the contact; Karyu Fig. 2C; [0064])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yoshimizu and Karyu before him/her, and form an insulating layer that electrically isolates the conductive contact , (1) because a sidewall insulating layer isolating the contact from all but the target conductive layer prevents shorting to non-target word lines; (2) since the modification amounts to a simple substitution of one known insulating collar for another of Karyu (MPEP 2144.06); and (3) with a reasonable expectation of success, yielding the predictable result of a single-layer electrical connection free of shorts to non-target word lines. Absent this teaching in Yoshimizu, a person with ordinary skill in the art would be motivated to reach out to Karyu while forming the conductive contact of Yoshimizu.
Allowable Subject Matter
No claim is presently indicated as containing allowable subject matter. The closest prior art of record, US 2021/0296239 A1 (Yoshimizu), discloses a contact that extends through two stacked memory-cell array layers and whose cross-section discontinuously changes at a boundary insulating layer such that the contact is narrower on the upper side and wider on the lower side — the very geometry recited by independent claims 1 and 11 — and further discloses the contact overlapping support structures. The dependent-claim features (a further stepped/neck portion, a separate upper-stack contact, support pillars arranged in the contact region, relative pillar densities, a thickest inter-deck insulating layer, and sidewall isolation) are taught or suggested by Hosotani, Watanabe1, and Karyu as set forth above.
Should Applicant amend to recite structure that the applied art does not reach — for example, a narrowed upper neck/third portion that is structurally and functionally distinct from the tier-boundary seam and that is shown to shield adjacent support structures during hole-bottom insulator removal, tied to specific dimensional relationships not disclosed by the applied references — such subject matter may place the application in condition for allowance. The Examiner invites a telephonic interview to identify allowable subject matter.
Examiner’s Note (Additional Prior Arts)
The Examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure:
Sun (US 2021/0287991 A1, Yangtze Memory) — Contact structures for 3D memory; stratified-depth contacts formed by repetitive mask-and-etch, with liner isolation and dummy strings.
Miyazaki (US 2020/0303407 A1, Kioxia) — Two-tier stacked bodies LMa/LMb with an inter-tier insulating layer 52 and stepped contacts CC penetrating a dummy stacked body LMd.
Watanabe2 (US 2021/0296227 A1, Kioxia) — Two-tier stack with first/second/third wiring portions and a separate second contact to upper-stack conductive layer 21b.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
08/06/2026
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