DETAILED ACTION
This is in response to communication received on 7/18/25.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of AIA 35 U.S.C. code not present in this action can be found in previous office actions dated 4/28/25, and 9/16/25.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/16/25 has been entered.
Claim Rejections - 35 USC § 103
The claim rejection(s) under AIA 35 U.S.C. 103 as being obvious over Ha et al. US PGPub 2015/0203961 hereinafter HA on claim 1, 7, 10, 12, and 15-16 are withdrawn because the independent claim 1 and 15 have been amended.
The claim rejection(s) under AIA 35 U.S.C. 103 as being obvious over Ha et al. US PGPub 2015/0203961 hereinafter HA and Lakshmanan et al. US PGPub 2013/0140698 hereinafter LAKSHMANAN on claim 2-6 are withdrawn because the independent claim 1 has been amended.
The claim rejection(s) under AIA 35 U.S.C. 103 as being obvious over Ha et al. US PGPub 2015/0203961 hereinafter HA and Wang et al. US PGPub 2018/0138085 hereinafter WANG on claim 8, 11 and 17 are withdrawn because the independent claim 1 has been been amended and claims 8 and have been cancelled.
The claim rejection(s) under AIA 35 U.S.C. 103 as being obvious over Ha et al. US PGPub 2015/0203961 hereinafter HA and Naik et al. US2018/0096888 hereinafter NAIK on claim 9, 13, 14 and 18-19 are withdrawn because the independent claim 1 and 18 have been amended.
The claim rejection(s) under AIA 35 U.S.C. 103 as being obvious over Ha et al. US PGPub 2015/0203961 hereinafter HA, Naik et al. US2018/0096888 hereinafter NAIK and Wang et al. US PGPub 2018/0138085 hereinafter WANG on claim 20 is withdrawn because the independent claim 18 has been amended.
Claim(s) 1, 7, 9-12, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. US PGPub 2015/0203961 hereinafter HA in view of Wang et al. US PGPub 2018/0138085 hereinafter WANG and Klawuhn et al US Patent Number 7,510,634 hereinafter KLAWUHN.
As for claim 1, HA teaches "Methods for forming a cobalt-ruthenium liner layer for copper interconnect structures are provided herein" (paragraph 16, lines 1-2), i.e. a method for forming an interconnect structure.
HA further teaches "The method 100 generally begins at 102, where the substrate 200 is exposed to a cobalt precursor 218 and to a ruthenium precursor 234 to form a cobalt-ruthenium layer 224 on the first surface 204 of the substrate 200 and on the sidewalls 210 and the bottom surface 208 of the opening 202" (paragraph 22, lines 1-5; as shown in figures 3A and 3B), i.e. depositing a ruthenium layer on a cobalt layer disposed on inner sidewalls of a feature formed on an interconnect layer on a substrate.
HA is silent on the term 'interconnect layer'. However, based upon the specification's discussion of interconnect layer, the 'interconnect layer' appears to be that of a conductive layer deposed within the substrate. As shown in Figures. Fig 3A and 3B, HA teaches "Further (and also illustrated by dotted lines), a conductive material (e.g., conductive material 220), for example as part of a device, such as a logic device or the like, or an electrical path to a device requiring electrical connectivity, such as a gate, a contact pad, a conductive line or via, or the like, may be disposed in the upper surface 226 of the second substrate 228 and aligned with the opening 202. In some embodiments, the conductive material (e.g., 220) aligned with the opening 202 may comprise copper" (paragraph 21, lines 715), wherein the conductive material is analogous to the interconnect layer of the claim such that HA teaches a cobalt layer disposed on inner walls of a feature formed on an interconnect layer on a substrate and directly on an exposed surface of the interconnect layer withing the feature.
HA is silent on while etching at least a portion of the cobalt layer formed in the feature.
WANG teaches "The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to etching cobalt during gapfill operations" (paragraph 1 ).
WANG further teaches “The deposition may include an overhang of cobalt extending past the sidewalls of the trench at an opening to the trench. This overhang of cobalt may constrict the trench width at the entrance to the trench, and in embodiments, the cobalt may completely pinch off or seal the trench from further deposition. Within the trench an amount of cobalt may be formed or deposited at the bottom of the trench and along the sidewalls. The trench may be only partially filled in embodiments before the trench opening is restricted or pinched off” (paragraph 40, lines 4-13) and "The methods may also include recessing the overhang of cobalt" (paragraph 5, lines 14-15), i.e. etching at least a portion of the cobalt layer.
WANG is silent on the etching taking place during the deposition.
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes while etching at least a portion of the cobalt layer formed in the feature because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. the ruthenium layer having a ruthenium concentration that increases from a lower portion of the feature to an upper portion of the feature.
HA further teaches "The cobalt-ruthenium liner layer described herein advantageously facilitates improved copper interconnect structures through one or more of improved copper reflow" (paragraph 16, lines 9-12), "The conductive material may include metals, metal alloys, or the like, such as one or more of copper (Cu)" (paragraph 33, lines 13-15), and "Next at 112, and as depicted in FIG. 2E, the conductive layer 230 may be heated, or annealed, to draw the deposited material into the opening 202 (for example, via capillary action). The heating process may be performed at a temperature ranging from about 150 to about 400 degrees Celsius. The cobalt-ruthenium layer advantageously allows for the conductive material to re-flow into, and fill, the opening without forming a void in the opening" (paragraph 34, lines 1 -8), i.e. depositing a copper layer within the feature, wherein a material forming the copper layer is heated to a reflow temperature before, during, or after depositing the copper layer.
As for claim 7, HA teaches "In some embodiments, the second period of time is sufficient to form the ruthenium layer 232 to a thickness of about 5 angstroms to about 10 angstroms" (paragraph 27, lines 23-25). It is expected that a person of ordinary skill in the art at the time of the invention could have converted the angstroms to a nm, which overlaps with the instant claimed range of wherein the ruthenium layer has a thickness of about 0.5 nanometers (nm) to about 5nm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d, 1362, 1365-66 (Fed. Cir.1997). See MPEP2144.05.
As for claim 9, HA teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. a ruthenium concentration gradient in the cobalt layer is formed from the top of the feature to the bottom of the feature after depositing the ruthenium layer.
HA is silent on wherein depositing the ruthenium layer is performed using a physical layer deposition (PVD) process.
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes wherein depositing the ruthenium layer is performed using a physical layer deposition (PVD) process because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
As for claim 10, HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. wherein depositing the ruthenium layer results in a ruthenium doped cobalt layer in at least a portion of the lower portion of the feature.
As for claim 11, HA is silent on wherein depositing the ruthenium layer further comprises etching at least a portion of the cobalt layer formed in the feature.
WANG teaches "The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to etching cobalt during gapfill operations" (paragraph 1 ).
WANG teaches that during deposition of cobalt into trenches "The methods may also include depositing additional cobalt in the trench, and producing a subsequent overhang" (paragraph 6, lines 9-11) and "The methods may also include recessing the overhang of cobalt" (paragraph 5, lines 14-15).
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes wherein depositing the ruthenium layer further comprises etching at least a portion of the cobalt layer formed in the feature because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
As for claim 12, HA teaches "Next at 112, and as depicted in FIG. 2E, the conductive layer 230 may be heated, or annealed, to draw the deposited material into the opening 202 (for example, via capillary action). The heating process may be performed at a temperature ranging from about 150 to about 400 degrees Celsius. The cobalt-ruthenium layer advantageously allows for the conductive material to re-flow into, and fill, the opening without forming a void in the opening" (paragraph 34, lines 1-8), i.e. a range that overlaps with wherein depositing the copper layer comprises at least heating the substrate to a temperature greater than 200°C. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d, 1362, 1365-66 (Fed. Cir.1997). See MPEP2144.05.
As for claim 15, HA teaches "Methods for forming a cobalt-ruthenium liner layer for copper interconnect structures are provided herein" (paragraph 16, lines 1-2), i.e. a method for forming an interconnect structure.
HA further teaches "The method 100 generally begins at 102, where the substrate 200 is exposed to a cobalt precursor 218 and to a ruthenium precursor 234 to form a cobalt-ruthenium layer 224 on the first surface 204 of the substrate 200 and on the sidewalls 210 and the bottom surface 208 of the opening 202" (paragraph 22, lines 1-5) and "In some embodiments, the substrate 200 may be covered with one or more layers prior to depositing the cobalt-ruthenium layer as described below. For example, the sidewalls 210 of the opening 202, the bottom surf ace 208 of the opening, and the first surface 204 of the substrate 200 may be covered by a barrier layer 216" (paragraph 20, lines 1-6), i.e. depositing a cobalt layer on a barrier layer disposed within a feature formed on ... a substrate.
HA is silent on the term 'interconnect layer'. However, based upon the specification's discussion of interconnect layer, the 'interconnect layer' appears to be that of a conductive layer deposed within the substrate. As shown in Figures. Fig 3A and 3B, HA teaches "Further (and also illustrated by dotted lines), a conductive material (e.g., conductive material 220), for example as part of a device, such as a logic device or the like, or an electrical path to a device requiring electrical connectivity, such as a
gate, a contact pad, a conductive line or via, or the like, may be disposed in the upper surface 226 of the second substrate 228 and aligned with the opening 202. In some embodiments, the conductive material (e.g., 220) aligned with the opening 202 may comprise copper" (paragraph 21, lines 715), and further that "the sidewalls 210 of the opening 202, the bottom surface 208 of the opening, and the first surface 204 of the substrate 200 may be covered by a barrier layer 216" (paragraph 20, lines 3-8), wherein the conductive material is analogous to the interconnect layer of the claim such that HA teaches a barrier layer disposed on inner walls of a feature formed on an interconnect layer on a substrate and directly on an exposed surface of the interconnect layer within the feature.
HA is silent on while etching at least a portion of the cobalt layer formed in the feature.
WANG teaches "The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to etching cobalt during gapfill operations" (paragraph 1 ).
WANG further teaches “The deposition may include an overhang of cobalt extending past the sidewalls of the trench at an opening to the trench. This overhang of cobalt may constrict the trench width at the entrance to the trench, and in embodiments, the cobalt may completely pinch off or seal the trench from further deposition. Within the trench an amount of cobalt may be formed or deposited at the bottom of the trench and along the sidewalls. The trench may be only partially filled in embodiments before the trench opening is restricted or pinched off” (paragraph 40, lines 4-13) and "The methods may also include recessing the overhang of cobalt" (paragraph 5, lines 14-15), i.e. etching at least a portion of the cobalt layer.
WANG is silent on the etching taking place during the deposition.
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes while etching at least a portion of the cobalt layer formed in the feature because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. depositing a ruthenium layer on the cobalt layer disposed within the feature, the ruthenium layer having a ruthenium concentration that increases from a lower portion of the feature to an upper portion of the feature.
HA further teaches "The cobalt-ruthenium liner layer described herein advantageously facilitates improved copper interconnect structures through one or more of improved copper reflow" (paragraph 16, lines 9-12), "The conductive material may include metals, metal alloys, or the like, such as one or more of copper (Cu)" (paragraph 33, lines 13-15), and "Next at 112, and as depicted in FIG. 2E, the conductive layer 230 may be heated, or annealed, to draw the deposited material into the opening 202 (for example, via capillary action). The heating process may be performed at a temperature ranging from about 150 to about 400 degrees Celsius. The cobalt-ruthenium layer advantageously allows for the conductive material to re-flow into, and fill, the opening without forming a void in the opening" (paragraph 34, lines 1-8), i.e. a range that overlaps with wherein depositing the copper layer comprises at least heating the substrate to a temperature greater than 200°C.
As for claim 16, HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. wherein depositing the ruthenium layer results in a ruthenium doped cobalt layer in at least a portion of the lower portion of the feature. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F .2d 257, 191 US PQ 90 ( CC PA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d, 1362, 1365-66 (Fed. Cir.1997). See MPEP2144.05.
Claim(s) 2-6 are rejected under 35 U.S.C. 103 as being unpatentable Ha et al. US PGPub 2015/0203961 hereinafter HA in view of Wang et al. US PGPub 2018/0138085 hereinafter WANG and Klawuhn et al US Patent Number 7,510,634 hereinafter KLAWUHN as applied to claim 1 above, and further in view of Lakshmanan et al. US PGPub 2013/0140698 hereinafter LAKSHMANAN.
As for claim 2, HA teaches "the sidewalls 210 of the opening 202, the bottom surface 208 of the opening, and the first surface 204 of the substrate 200 may be covered by a barrier layer 216" (paragraph 20, lines 4-6) wherein the barrier layer, when present, is deposed directly on top of the interconnect layer beneath the feature. Thereby, when the barrier layer of HA is present, the cobalt cannot be directly on an exposed surface of the interconnect layer within the feature.
LAKSHMANAN teaches "The present invention relates generally to barrier layers in semiconductor devices, and methods of forming such barrier layers. More particularly, the disclosed method relates to films comprising TaN and selected dopants" (paragraph 2) and "One aspect of the current invention pertains to a method for forming interconnections in a microelectronic device" (paragraph 6, lines 1-3).
LAKSHMANAN teaches "depositing a barrier layer comprising TaN and one or more dopants on at least a portion of the sidewall and/or bottom of the trench" (paragraph 6, lines 6-8) and "FIG.1 B shows the same microelectronic device 100 after deposition of a barrier layer 130, which covers at least a portion of the sidewall 115 and/or trench bottom 120. As shown in FIG. 1 B, the barrier layer 130 may cover the entirety of the sidewall 115 and trench bottom 120" (paragraph 23, lines 1-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the barrier layer of HA only to the sidewall such that it includes further comprising depositing the cobalt layer on a barrier layer disposed within on the inner sidewalls of the feature and a cobalt layer disposed ... and directly on an exposed surface of the interconnect layer within the feature because LAKSHMANAN teaches that such a configuration was a known alternative to the complete barrier coating of HA.
As for claim 3, HA teaches "Methods for forming a cobalt-ruthenium liner layer for copper interconnect structures are provided herein. A "liner layer," as used herein, may refer to a layer conformably formed along at least a portion of the sidewalls and/or lower surface of an opening" (paragraph 1-6), i.e. wherein the cobalt layer comprises a conformal layer covering a surface of the barrier layer.
As for claim 4, HA teaches "The first period of time and second period of time are sufficient to form the cobalt-ruthenium layer 224 to a suitable thickness, for example a thickness of less than about 20 angstroms. In some embodiments, the first period of time is sufficient to form the cobalt layer 222 to a thickness of about 10 angstroms to about 15 angstroms" (paragraph 27, lines 17-23). It is expected that a person of ordinary skill in the art at the time of the invention could have converted the angstroms to a nm, which overlaps with the instant claimed range of wherein the cobalt layer has a thickness of about 0.5 nanometers (nm) to about 3nm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d, 1362, 1365-66 (Fed. Cir.1997). See MPEP2144.05.
As for claim 5, HA teaches "The barrier layer 216 may comprise any material suitable to act as a barrier. For example, in some embodiments, the barrier layer 216 may comprise a metal, for example ... tantalum (Ta) ... or in some embodiments, a metal nitride, such as ... tantalum nitride (TaN)" (paragraph 20, lines 9-15), i.e. wherein the barrier layer comprises at least one of tantalum, tantalum nitride, and ruthenium.
As for claim 6, HA teaches "In some embodiments, the cobalt-ruthenium layer 224 may be formed via a plasma assisted deposition process, such as a plasma enhanced chemical vapor deposition process, or a thermal chemical vapor deposition process" (paragraph 26, lines 1-4), i.e. wherein the cobalt layer is deposited using chemical layer deposition (CVD) or a plasma enhanced CVD (PECVD) process.
Claim(s) 13, 14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. US PGPub 2015/0203961 hereinafter HA in view of Wang et al. US PGPub 2018/0138085 hereinafter WANG and Klawuhn et al US Patent Number 7,510,634 hereinafter KLAWUHN as applied to claim 1 above, and further in view of Naik et al. US2018/0096888 hereinafter NAIK.
As for claim 13, HA is silent on further comprising removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer.
NAIK teaches "The thickness of the metal fill layer 110 is properly chosen to serve as a basis for the subsequent CM P process. Thereafter, the excessive metal fill layer 110 is etched back using a chemical mechanical polishing (CMP) process to expose a top surface 107 of the substrate 100, a top surf ace 109 of the barrier layer 106 (if used), and a top surface 111 of the intermediate layer 108. Therefore, the top surface 107 of the substrate 100, the top surface 109 of the barrier layer 106 (if .used), the top surface 111 of the intermediate layer 108 and a top surface 103 of the metal fill layer 110 are substantially co-planar, as shown in FIG. 2C" (paragraph 29, lines 16-27) which shows removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer.
NAIK teaches that after the planarization there is the application of a metal cap layer (paragraph 30) and "The metal cap layer 114 is believed to improve electromigration performance of the underlying copper filling by increasing Cu and dielectric barrier adhesion" (paragraph 30, lines 10-13).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include further comprising removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer in the process of HA because NAIK teaches that a process that includes such a step allows for the creation of a metal cap layer that improves the electro-migration performing of the underlying copper filing.
As for claim 14, HA is silent on wherein removing the portion of the interconnect structure is performed using chemical-mechanical planarization (CMP).
NAIK teaches "The thickness of the metal fill layer 110 is properly chosen to serve as a basis for the subsequent CM P process. Thereafter, the excessive metal fill layer 110 is etched back using a chemical mechanical polishing (CM P) process to expose a top surface 107 of the substrate 100, a top surf ace 109 of the barrier layer 106 (if used), and a top surface 111 of the intermediate layer 108. Therefore, the top surface 107 of the substrate 100, the top surface 109 of the barrier layer 106 (if .used), the top surface 111 of the intermediate layer 108 and a top surface 103 of the metal fill layer 110 are substantially co-planar, as shown in FIG. 2C" (paragraph 29, lines 16-27) which includes wherein removing the portion of the interconnect structure is performed using chemical-mechanical planarization (CMP).
NAIK teaches that after the planarization there is the application of a metal cap layer (paragraph 30) and "The metal cap layer 114 is believed to improve electromigration performance of the underlying copper filling by increasing Cu and dielectric barrier adhesion" (paragraph 30, lines 10-13).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include wherein removing the portion of the interconnect structure is performed using chemical-mechanical planarization (CMP) in the process of HA because NAIK teaches that a process that includes such a step allows for the creation of a metal cap layer that improves the electro-migration performing of the underlying copper filing.
As for claim 18, HA teaches "Methods for forming a cobalt-ruthenium liner layer for copper interconnect structures are provided herein" (paragraph 16, lines 1-2), i.e. a method for forming an interconnect structure.
HA further teaches "The method 100 generally begins at 102, where the substrate 200 is exposed to a cobalt precursor 218 and to a ruthenium precursor 234 to form a cobalt-ruthenium layer 224 on the first surface 204 of the substrate 200 and on the sidewalls 210 and the bottom surface 208 of the opening 202" (paragraph 22, lines 1-5), i.e. depositing a ruthenium layer on a cobalt layer disposed within a feature formed on ... a substrate.
HA is silent on the term 'interconnect layer'. However, based upon the specification's discussion of interconnect layer, the 'interconnect layer' appears to be that of a conductive layer deposed within the substrate. As shown in Figures. Fig 3A and 3B, HA teaches "Further (and also illustrated by dotted lines), a conductive material (e.g., conductive material 220), for example as part of a device, such as a logic device or the like, or an electrical path to a device requiring electrical connectivity, such as a gate, a contact pad, a conductive line or via, or the like, may be disposed in the upper surface 226 of the second substrate 228 and aligned with the opening 202. In some embodiments, the conductive material (e.g., 220) aligned with the opening 202 may comprise copper" (paragraph 21, lines 715), wherein the conductive material is analogous to the interconnect layer of the claim such that HA teaches a cobalt layer disposed on inner walls of a feature formed on an interconnect layer on a substrate and directly on an exposed surface of the interconnect layer withing the feature.
HA is silent on while etching at least a portion of the cobalt layer formed in the feature.
WANG teaches "The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to etching cobalt during gapfill operations" (paragraph 1 ).
WANG further teaches “The deposition may include an overhang of cobalt extending past the sidewalls of the trench at an opening to the trench. This overhang of cobalt may constrict the trench width at the entrance to the trench, and in embodiments, the cobalt may completely pinch off or seal the trench from further deposition. Within the trench an amount of cobalt may be formed or deposited at the bottom of the trench and along the sidewalls. The trench may be only partially filled in embodiments before the trench opening is restricted or pinched off” (paragraph 40, lines 4-13) and "The methods may also include recessing the overhang of cobalt" (paragraph 5, lines 14-15), i.e. etching at least a portion of the cobalt layer.
WANG is silent on the etching taking place during the deposition.
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes while etching at least a portion of the cobalt layer formed in the feature because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. the ruthenium layer having a ruthenium concentration that increases from a lower portion of the feature to an upper portion of the feature.
HA further teaches "The cobalt-ruthenium liner layer described herein advantageously facilitates improved copper interconnect structures through one or more of improved copper reflow" (paragraph 16, lines 9-12), "The conductive material may include metals, metal alloys, or the like, such as one or more of copper (Cu)" (paragraph 33, lines 13-15), and "Next at 112, and as depicted in FIG. 2E, the conductive layer 230 may be heated, or annealed, to draw the deposited material into the opening 202 (for example, via capillary action). The heating process may be performed at a temperature ranging from about 150 to about 400 degrees Celsius. The cobalt-ruthenium layer advantageously allows for the conductive material to re-flow into, and fill, the opening without forming a void in the opening" (paragraph 34, lines 1 -8), i.e. depositing a copper layer within the feature, wherein a material forming the copper layer is heated to a ref/ow temperature before, during, or after depositing the copper layer.
HA is silent on further comprising removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer.
NAIK teaches "The thickness of the metal fill layer 110 is properly chosen to serve as a basis for the subsequent CMP process. Thereafter, the excessive metal fill layer 110 is etched back using a chemical mechanical polishing (CMP) process to expose a top surface 107 of the substrate 100, a top surface 109 of the barrier layer 106 (if used), and a top surface 111 of the intermediate layer 108. Therefore, the top surface 107 of the substrate 100, the top surface 109 of the barrier layer 106 (if .used), the top surface 111 of the intermediate layer 108 and a top surface 103 of the metal fill layer 110 are substantially co-planar, as shown in FIG. 2C" (paragraph 29, lines 16-27) which shows removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer.
NAIK teaches that after the planarization there is the application of a metal cap layer (paragraph 30) and "The metal cap layer 114 is believed to improve electromigration performance of the underlying copper filling by increasing Cu and dielectric barrier adhesion" (paragraph 30, lines 10-13).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include further comprising removing a portion of the interconnect structure, the portion of the interconnect structure comprising an upper portion of the ruthenium layer in the process of HA because NAIK teaches that a process that includes such a step allows for the creation of a metal cap layer that improves the electro-migration performing of the underlying copper filing.
As for claim 19, HA further teaches "the cobalt layer material may decrease in concentration from the interface to the opposing surface of the cobalt-ruthenium layer 224 and the ruthenium layer material may increase in concentration from the interface to the opposing surface of the cobalt-ruthenium layer" (paragraph 30, lines 5-9), i.e. wherein depositing the ruthenium layer results in a ruthenium doped cobalt layer in the lower portion of the feature.
As for claim 20, HA is silent on wherein depositing the ruthenium layer further comprises etching the cobalt layer.
WANG teaches "The present technology relates to semiconductor processes and equipment. More specifically, the present technology relates to etching cobalt during gapfill operations" (paragraph 1 ).
WANG teaches that during deposition of cobalt into trenches "The methods may also include depositing additional cobalt in the trench, and producing a subsequent overhang" (paragraph 6, lines 9-11) and "The methods may also include recessing the overhang of cobalt" (paragraph 5, lines 14-15).
Examiner does note that HA also teaches “The method 100 may be performed in any suitable process chambers configured for one or more of… physical vapor deposition (PVD)” (paragraph 17, lines 5-9) and WANG teaches “Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to… physical vapor deposition (PVD)” (paragraph 23, lines 11-16).
KLAWUHN teaches “Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer” (abstract, lines 1-3).
KLAWUHN further teaches “The deposition and subsequent resputtering process are most often used, respectively, for deposition and resputtering of the diffusion barrier layer, but can also be employed in the deposition or etch-back of other wafer materials such as conductive metal layers; e.g., copper seed layers. That is, selective deposition of trenches and vias can be applied to any suitable material. Diffusion barrier materials commonly subjected to deposition and subsequent resputtering include but are not limited to… ruthenium, cobalt” (column 4, line 59 – column 5, line 2).
KLAWUHN further teaches “An Ionized Physical Deposition (iPVD) process may be used for deposition and resputtering of a material. That is, a same iPVD chamber, as described further below, may be used both deposit and remove a material with respect to a recessed feature. An important characteristic of iPVD processes is the etch rate to deposition rate ratio (E/D). It should be understood, that both etching and depositing processes are occurring simultaneously during deposition or resputter. Deposition is the result of inert gas particles bombarding the target, and sputtering target material (neutral or ionic) onto the wafer surface. Etching is the result of inert gas particles bombarding the wafer. In some embodiments of this invention, ionized metal may be used together with ionized gas for resputtering of wafer materials.” (column 5, lines 7-17), i.e. etching and depositing at the same time.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the etching and depositing process of KLAWUHN in the process of HA to recess the cobalt overhang as taught by WANG such that it includes wherein depositing the ruthenium layer further comprises etching the cobalt layer because WANG teaches that removing the overhang ensures that the trench is properly filled and not pinched off and KLAWUHN teaches that its process allows for simultaneous etching and deposition while protecting other part of the substrate.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 9-16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/KRISTEN A DAGENAIS/Examiner, Art Unit 1717