Prosecution Insights
Last updated: October 02, 2026
Application No. 18/593,716

APPLICATION PROGRAMMING INTERFACE TO STORE IDENTIFIERS OF MULTIPROCESSOR GROUPS

Non-Final OA §102
Filed
Mar 01, 2024
Priority
Jan 25, 2024 — provisional 63/625,278
Examiner
BARHAM, RYAN ALLEN
Art Unit
2613
Tech Center
2600 — Communications
Assignee
NVIDIA Corporation
OA Round
3 (Non-Final)
53%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 53% of resolved cases
53%
Career Allowance Rate
9 granted / 17 resolved
-9.1% vs TC avg
Strong +57% interview lift
Without
With
+57.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
24 currently pending
Career history
44
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
39.4%
-0.6% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/01/2026 has been entered. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/07/2026 was filed after the mailing date of the final Office action on 04/01/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Munshi (US 10067797 B2). Regarding claim 1, Munshi teaches one or more processors, comprising: circuitry to, in response to an application programming interface (API) call indicating a plurality of streaming multiprocessors (SMs), at least: generate information identifying a plurality of groups of SMs, wherein each group comprises a subset of the plurality of SMs (col. 15, lines 19-23: “In one embodiment, API calls to a compute runtime to execute a compute kernel may include the number of threads that execute simultaneously in parallel on a compute processor as a thread group. An API call may include the number of compute processors to use.”); and return the information as a result of the API call, wherein the information enables selection of one or more groups of SMs of the plurality of groups of SMs to perform one or more software kernels (col. 15, line 63 – col. 16, line 8: “At block 517, in one embodiment, the processing logic of process 500 may select one of the plurality of executables loaded to the compute kernel object corresponding to the selected compute kernel instance for execution in a physical computing device associated with the logical computing device for the compute kernel object. The processing logic of process 500 may select more than one executables to be executed in more than one physical computing devices in parallel for one compute kernel execution instance. The selection may be based on current execution statuses of the physical computing devices corresponding to the logical computing device associated with the selected compute kernel execution instance.”). Regarding claim 2, Munshi teaches the one or more processors of claim 1, wherein the API call indicates a memory location (col. 11, line 57 – col. 12, line 36: “The application may send the compute capability requirement to a system application by calling APIs. The system application may correspond to a platform layer of a software stack in a hosting system for the application. In one embodiment, a compute capability requirement may identify a list of required capabilities for requesting processing resources to perform a task for the application. In one embodiment, the application may require the requested processing resources to perform the task in multiple threads concurrently. In response, the processing logic of process 400 may select a group of physical computing devices from attached physical computing devices at block 405. The selection may be determined based on a matching between the compute capability requirement against the compute capabilities stored in the capability data structure.”) usable to store a group of identifiers corresponding to the one or more groups of SMs of the plurality of groups of SMs (col. 12, lines 52-63: “At block 407, in one embodiment, the processing logic of process 400 may generate a computing device identifier for each group of physical computing devices selected at block 405. The processing logic of process 400 may return one or more of the generated computing device identifiers back to the application through the calling APIs. An application may choose which processing resources to employ for performing a task according to the computing device identifiers. In one embodiment, the processing logic of process 400 may generate at most one computing device identifier at block 407 for each capability requirement received.”). Regarding claim 3, Munshi teaches the one or more processors of claim 1, wherein the generated information comprises a plurality of identifiers corresponding to the one or more groups of SMs (col. 15, lines 19-31: “In one embodiment, API calls to a compute runtime to execute a compute kernel may include the number of threads that execute simultaneously in parallel on a compute processor as a thread group. An API call may include the number of compute processors to use. A compute kernel execution instance may include a priority value indicating a desired priority to execute the corresponding compute program executable. A compute kernel execution instance may also include an event object identifying a previous execution instance and/or expected total number of threads and number of thread groups to perform the execution. The number of thread groups and total number of threads may be specified in the API calls.”). Regarding claim 4, Munshi teaches the one or more processors of claim 1, the circuity further to: generate masks to indicate the one or more groups of SMs of the plurality of groups of SMs to perform the one or more software kernels (col. 18, lines 38-41, w/rt Fig. 8: “FIG. 8 is a flow diagram illustrating one embodiment of a process 800 to determine optimal thread group sizes to concurrently execute compute kernel objects among multiple compute units.”). Regarding claim 5, Munshi teaches the one or more processors of claim 1, wherein the API call indicates a set of flags identifying the one or more groups of SMs to be selected of the plurality of groups of SMs to perform the one or more software kernels (col. 15, lines 1-9, w/rt Fig. 1: “The processing logic of process 500 may execute a computer kernel in response to API calls with appropriate arguments to a compute runtime, e.g. compute runtime 109 of FIG. 1, from an application or a compute application library, such as applications 103 or compute application library 105 of FIG. 1. Executing a compute kernel may include executing a compute program executable associated with the compute kernel.”). Regarding claim 6, Munshi teaches the one or more processors of claim 1, wherein the API call indicates a minimum count of a number of SMs of the one or more groups of SMs of the plurality of groups of SMs (col. 8-11, TABLE 2: “CL_DEVICE_MAX_WRITE_IMAGE_ARGS1 | Max number of simultaneous image memory objects that can be written to by a compute kernel. The minimum value is 0 if the computing device does not support formatted image writes. If formatted image writes are supported, the minimum value is 8.”). Regarding claim 7, Munshi teaches the one or more processors of claim 1, the circuitry to further: allocate a memory location to return one or more values indicating that a plurality of identifiers, corresponding to the one or more groups of SMs, have been stored (col. 12, line 64 – col. 13, line 7: “At block 409, in one embodiment, the processing logic of process 400 may allocate resources to initialize a logical computing device for a group of physical computing devices selected at block 405 according to a corresponding computing device identifier. A logical computing device may be a computing device group including one or more physical computing devices. The processing logic of process 400 may perform initializing a logical computing device in response to API requests from an application which has received one or more computing device identifiers according to the selection at block 405.”). Claim 8 is substantially similar to claim 1, and differs only in that it outlines a computer-implemented method rather than one or more processors. As such, it is rejected on a similar basis to claim 1. Claim 9 is substantially similar to claim 2, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 2. Claim 10 is substantially similar to claim 3, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 3. Claim 11 is substantially similar to claim 4, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 4. Claim 12 is substantially similar to claim 5, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 5. Claim 13 is substantially similar to claim 6, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 6. Claim 14 is substantially similar to claim 7, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 7. Claim 15 is substantially similar to claim 1, and differs only in that it outlines a computer system rather than one or more processors. As such, it is rejected on a similar basis to claim 1. Claim 16 is substantially similar to claim 2, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 2. Claim 17 is substantially similar to claim 3, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 3. Claim 18 is substantially similar to claim 4, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 4. Claim 19 is substantially similar to claim 5, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 5. Claim 20 is substantially similar to claim 6, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 6. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A BARHAM whose telephone number is (571)272-4338. The examiner can normally be reached Mon-Fri, 8:30am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu, can be reached at (571) 272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN ALLEN BARHAM/Examiner, Art Unit 2613 /XIAO M WU/Supervisory Patent Examiner, Art Unit 2613
Read full office action

Prosecution Timeline

Mar 01, 2024
Application Filed
May 15, 2024
Response after Non-Final Action
Nov 13, 2025
Non-Final Rejection mailed — §102
Feb 12, 2026
Response Filed
Apr 01, 2026
Final Rejection mailed — §102
Jul 01, 2026
Request for Continued Examination
Jul 05, 2026
Response after Non-Final Action
Aug 10, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
53%
Grant Probability
99%
With Interview (+57.1%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 17 resolved cases by this examiner. Grant probability derived from career allowance rate.

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