Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4, line 2: “the circuitry further to” should read “the circuitry to further”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Munshi (US 10067797 B2).
Regarding claim 1, Munshi teaches one or more processors, comprising:
circuitry to:
in response to an application programming interface (API) call, cause a plurality of identifiers corresponding to a plurality of groups of streaming multiprocessors (SMs) of one or more processors to be stored, in which use of an identifier of the plurality of identifiers enables selection of a corresponding group of SMs of the plurality of groups of SMs to perform one or more software kernels (col. 1, line 62 – col. 2, line 6: “An embodiment of the present invention includes methods and apparatuses for a parallel computing program calling APIs in a host processor to perform a data processing task in parallel among compute units including central processing units (CPUs) and graphic processing units (GPUs) coupled to the host processor. A program object corresponding to a source code for the data processing task is generated in a memory coupled to the host processor according to the API calls. Executable codes for the compute units are generated from the program object according to the API calls to be loaded for concurrent execution among the compute units to perform the data processing task.” NOTE: The term “compute units” is considered analogous to the term “streaming multiprocessors”).
Regarding claim 2, Munshi teaches the one or more processors of claim 1, wherein the API call comprises arguments indicating a memory location (col. 11, line 57 – col. 12, line 36: “The application may send the compute capability requirement to a system application by calling APIs. The system application may correspond to a platform layer of a software stack in a hosting system for the application. In one embodiment, a compute capability requirement may identify a list of required capabilities for requesting processing resources to perform a task for the application. In one embodiment, the application may require the requested processing resources to perform the task in multiple threads concurrently. In response, the processing logic of process 400 may select a group of physical computing devices from attached physical computing devices at block 405. The selection may be determined based on a matching between the compute capability requirement against the compute capabilities stored in the capability data structure.”) usable to store a group of identifiers of the plurality of identifiers corresponding to the group of SMs of the plurality of groups of SMs (col. 12, lines 52-63: “At block 407, in one embodiment, the processing logic of process 400 may generate a computing device identifier for each group of physical computing devices selected at block 405. The processing logic of process 400 may return one or more of the generated computing device identifiers back to the application through the calling APIs. An application may choose which processing resources to employ for performing a task according to the computing device identifiers. In one embodiment, the processing logic of process 400 may generate at most one computing device identifier at block 407 for each capability requirement received.”).
Regarding claim 3, Munshi teaches the one or more processors of claim 1, wherein the API call comprises arguments indicating a memory location (col. 11, line 57 – col. 12, line 36, as above in claim 2 rejection) usable to store a second plurality of identifiers corresponding to one or more second groups of the plurality of groups of SMs (col. 15, lines 19-31: “In one embodiment, API calls to a compute runtime to execute a compute kernel may include the number of threads that execute simultaneously in parallel on a compute processor as a thread group. An API call may include the number of compute processors to use. A compute kernel execution instance may include a priority value indicating a desired priority to execute the corresponding compute program executable. A compute kernel execution instance may also include an event object identifying a previous execution instance and/or expected total number of threads and number of thread groups to perform the execution. The number of thread groups and total number of threads may be specified in the API calls.”).
Regarding claim 4, Munshi teaches the one or more processors of claim 1, the circuity further to:
generate masks to indicate the group of SMs of the plurality of groups of SMs to perform the one or more software kernels (col. 18, lines 38-41, w/rt Fig. 8: “FIG. 8 is a flow diagram illustrating one embodiment of a process 800 to determine optimal thread group sizes to concurrently execute compute kernel objects among multiple compute units.”).
Regarding claim 5, Munshi teaches the one or more processors of claim 1, wherein the API call comprises arguments indicating a set of flags identifying the group of SMs to be selected of the plurality of groups of SMs to perform the one or more software kernels (col. 15, lines 1-9, w/rt Fig. 1: “The processing logic of process 500 may execute a computer kernel in response to API calls with appropriate arguments to a compute runtime, e.g. compute runtime 109 of FIG. 1, from an application or a compute application library, such as applications 103 or compute application library 105 of FIG. 1. Executing a compute kernel may include executing a compute program executable associated with the compute kernel.”).
Regarding claim 6, Munshi teaches the one or more processors of claim 1, wherein the API call comprises arguments indicating a minimum count of a number of SMs of at least one group of the plurality of groups of SMs (col. 8-11, TABLE 2: “CL_DEVICE_MAX_WRITE_IMAGE_ARGS1 | Max number of simultaneous image memory objects that can be written to by a compute kernel. The minimum value is 0 if the computing device does not support formatted image writes. If formatted image writes are supported, the minimum value is 8.”).
Regarding claim 7, Munshi teaches the one or more processors of claim 1, the circuitry to further:
allocate a memory location to return one or more values indicating that the plurality of identifiers have been stored (col. 12, line 64 – col. 13, line 7: “At block 409, in one embodiment, the processing logic of process 400 may allocate resources to initialize a logical computing device for a group of physical computing devices selected at block 405 according to a corresponding computing device identifier. A logical computing device may be a computing device group including one or more physical computing devices. The processing logic of process 400 may perform initializing a logical computing device in response to API requests from an application which has received one or more computing device identifiers according to the selection at block 405.”).
Claim 8 is substantially similar to claim 1, and differs only in that it outlines a computer-implemented method rather than one or more processors. As such, it is rejected on a similar basis to claim 1.
Claim 9 is substantially similar to claim 2, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 2.
Claim 10 is substantially similar to claim 3, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 3.
Claim 11 is substantially similar to claim 4, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 4.
Claim 12 is substantially similar to claim 5, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 5.
Claim 13 is substantially similar to claim 6, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 6.
Claim 14 is substantially similar to claim 7, and differs only in that it depends from claim 8 rather than claim 1. As such, it is rejected on a similar basis to claim 7.
Claim 15 is substantially similar to claim 1, and differs only in that it outlines a computer system rather than one or more processors. As such, it is rejected on a similar basis to claim 1.
Claim 16 is substantially similar to claim 2, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 2.
Claim 17 is substantially similar to claim 3, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 3.
Claim 18 is substantially similar to claim 4, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 4.
Claim 19 is substantially similar to claim 5, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 5.
Claim 20 is substantially similar to claim 6, and differs only in that it depends from claim 15 rather than claim 1. As such, it is rejected on a similar basis to claim 6.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN ALLEN BARHAM/Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613