Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Yang (US 20220338356).
Regarding claim 19, Yang discloses a method, comprising:
fabricating a printed circuit board (PCB 20, Fig. 11) with a first trace layer (wiring layer 22) disposed on a first surface of the PCB and a second trace layer (wiring layer 21) disposed on a second surface of the PCB, wherein the first surface comprises a primary component footprint (the footprint of component 73), and the second surface comprises a secondary component footprint (footprint of component 71);
mounting an electronic component (mount component 73) to the primary component footprint without mounting an additional electronic component (mount component 71) to the secondary component footprint; and
configuring the PCB to operate in a first operating configuration selected from at least two operating configurations, wherein the first operating configuration corresponds to utilization of the primary component footprint, and the at least two operating configurations include a second operating configuration corresponding to utilization of the secondary component footprint (the components are arranged in a configuration to provide a functional circuit board).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 6, 8 – 11, 14 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman (US 8124429), in view of Kariyazaki (US 20180098420).
Regarding claim 1, Norman discloses a circuit board, comprising:
a first non-conductive layer (some of the top dielectric layers 130, Fig. 1) and a second non-conductive layer (some of the bottom dielectric layers 120’ or 130);
a first electronic component (left side component 111),
wherein the circuit board is configurable to operate in a first configuration (the configuration of the top layer involving several components 111) with a second electronic component (the right side component 111), and
the circuit board is configurable to operate in a second configuration (the configuration involving the component 121 in the middle layer between top layers and bottom layers) with a third electronic component (the left side component 121 connected to the left side component 111) instead of the second electronic component;
a second trace layer (the conductive layer having the traces connecting the left side component 111 to the left side component 121) disposed between the first non-conductive layer and the second non-conductive layer, wherein the second trace layer is configured to electrically couple the first electronic component (left side component 111) to the third electronic component (left side component 121) in the second configuration of the circuit board.
Norman does not explicitly disclose a first trace layer disposed on the first non-conductive layer, wherein the first trace layer is configured to electrically couple the first electronic component to the second electronic component in the first configuration of the circuit board.
Kariyazaki teaches a first trace layer (the layer of trace connecting chip 30A and 30B together, Fig. 4) disposed on the first non-conductive layer, wherein the first trace layer is configured to electrically couple the first electronic component (30A) to the second electronic component (30B) in the first configuration (Fig. 4 or Fig. 7) of the circuit board.
It would have been obvious to one having skill in the art at the effective filing date of the invention to connect the components on the circuit using conductive traces in order to form the intended circuitry.
Regarding claim 2, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1. Norman further suggests the circuit board is configurable to operate in a third configuration (the configuration of one of the layers near the bottom side, Fig. 1, including component 121’) with a fourth electronic component (left side component 121’) instead of the second electronic component or the third electronic component, the circuit board comprises a third trace layer (the trace layer connected to the left side component 121’) disposed on the second non-conductive layer, and the third trace layer is configured to electrically couple the first electronic component (left side component 111) to the fourth electronic component (left side component 121’) in the third configuration of the circuit board.
Regarding claim 3, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 2. Norman further suggests the first non-conductive layer is disposed between the first trace layer and the second trace layer (the top substrate is disposed between the top conductive layer and the middle conductive layer), and the second non-conductive layer (one of the bottom substrate 120’ is disposed between the middle conductive layer and the bottom conductive layer) is disposed between the second trace layer and the third trace layer.
Regarding claim 4, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1. Norman further suggests the first non-conductive layer comprises a first surface (top surface of the top substrate 130) and a second surface (bottom surface of the top substrate 130), the second non-conductive layer (bottom 121’ or 130) comprises a third surface (top surface) and a fourth surface (bottom surface), the first trace layer is disposed on the first surface (top surface of the top layer 130), and the second trace layer is disposed between the second surface (bottom surface of the top layer 130) and the third surface (top surface of the bottom layer 121’ or 130).
Regarding claim 5, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1. Norman further suggests the first electronic component is configured to communicate with the second electronic component via a first communication protocol (the connection between the top left component 111 with the other components 111 suggested by the top surface network of Kariyazaki) in the first configuration, and the first electronic component is configured to communicate with the third electronic component via a second communication protocol (the connection between the top left component 111 with the middle left component 121) in the second configuration.
Regarding claim 6, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 5. Norman further suggests the first electronic component is configured to utilize the first communication protocol or the second communication protocol based on respective signals received from the second electronic component and the third electronic component, respectively.
Regarding claim 8, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1. Norman further suggests the first electronic component is configured to: determine a reference voltage (every circuitry, at any point, is operating at a certain voltage reference) at a location on the circuit board; and determine that the circuit board is configured to operate in the first configuration or the second configuration based on the reference voltage (the reference voltage at different location of the circuitry may be different from each other).
Regarding claim 9, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 8. Norman further suggests the first electronic component is configured to operate in a first operating mode in response to a determination that the circuit board is configured to operate in the first configuration (each section of a circuitry has its own function to be considered as a configuration for that section); and operate in a second operating mode in response to a determination that the circuit board is configured to operate in the second configuration (each section of a circuitry has its own function to be considered as a configuration for that section).
Regarding claim 10, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 8.
Norman does not explicitly disclose a voltage divider configured to produce the reference voltage.
Kariyazaki suggests a voltage conversion circuit CVT in the logic chip 30B, paragraph 220.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a voltage conversion or voltage divider in order to adjust the reference voltage at a particular point in the circuitry.
Regarding claim 11, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 10. Kariyazaki suggests the voltage divider is configured to: receive an input voltage (a voltage conversion circuit inherently include an input side) from the second electronic component or the third electronic component; and output (the voltage conversion circuit inherently include an output side) the reference voltage to a reference voltage pin of the first electronic component.
Regarding claim 14, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1. Kariyazaki suggests the first trace layer comprises a first trace segment extending from a first footprint (a variety configuration of the footprint and traces in Figures 7 - 18) of the first electronic component, the first trace layer comprises a second trace segment extending from a second footprint (a variety configuration of the footprint and traces in Figures 7 - 18) of the second electronic component, the second trace layer comprises a third trace segment extending from a third footprint of the third electronic component, and the circuit board comprises a via extending from the third trace segment to the first trace layer (the connection between the components are extending from the footprint of the component, as suggested by Kariyazaki).
Regarding claim 15, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 1.
Norman does not explicitly disclose the first electronic component is a microcontroller.
Kariyazaki suggests the component 30 is a controller chip (paragraph 57). Norman also suggests the components are in a micro scale and one of the components is a microprocessor (in the summary of the prior art, and the definition section).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a microcontroller in the circuitry to calculate all the parameter and to make sure the circuitry is operating as intended.
Regarding claim 16, Norman discloses a circuit board, comprising:
one of a primary electronic component (the left side component 111, Fig. 1) or a secondary electronic component (the right side component 111);
a second trace layer (the conductive layer having the traces connecting the left side component 111 to the left side component 121) formed on a second surface (the surface having components 121) of the circuit board, opposite the first surface, wherein:
the second surface comprises a secondary component footprint (footprint of the component 111) corresponding to the secondary electronic component, the circuit board is configurable to operate in a first configuration (the configuration having component 111) associated with installation of the primary electronic component on the primary component footprint; and
the circuit board is configurable to operate in a second configuration associated with installation of the secondary electronic component (installing the component 111 on its footprint) on the secondary component footprint.
Norman does not explicitly disclose a microcontroller; a first trace layer formed on a first surface of the circuit board, wherein the first surface comprises a primary component footprint corresponding to the primary electronic component.
Kariyazaki suggests the component 30 is a controller chip (paragraph 57). Norman also suggests the components are in a micro scale and one of the components is a microprocessor (in the summary of the prior art, and the definition section).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a microcontroller in the circuitry to calculate all the parameter and to make sure the circuitry is operating as intended.
Kariyazaki teaches a first trace layer (traces and footprint in Figures 7 - 18) formed on a first surface of the circuit board, wherein the first surface comprises a primary component footprint (component 30A) corresponding to the primary electronic component.
It would have been obvious to one having skill in the art at the effective filing date of the invention to connect the components on the circuit using conductive traces in order to form the intended circuitry.
Regarding claim 17, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 16. Kariyazaki further suggests the microcontroller is configured to: determine that the circuit board is in the first configuration; and communicate with the primary electronic component using a first communication protocol in response to determining that the circuit board is in the first configuration (the controller inherently calculating all the parameter in the circuitry).
Regarding claim 18, Norman, in view of Kariyazaki, discloses the claimed invention as set forth in claim 16. Kariyazaki further suggests the primary electronic component is an integrated circuit comprising a plurality of pins (multiple solder balls or pins and footprint for the pins; Fig. 3 and Fig. 7), and the primary component footprint comprises a plurality of solder pads (solder balls 11 and 35; Fig. 5. Pad 25 for the solder balls) corresponding to the plurality of pins.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220338356), in view of Kariyazaki (US 20180098420).
Regarding claim 20, Yang discloses the claimed invention as set forth in claim 19.
Yang does not explicitly disclose configuring the PCB to operate in the first operating configuration by applying solder to a solder bridge footprint, wherein solder bridge footprint is formed on the first surface, the second surface, or a third surface of the PCB.
Rariyazaki suggests the solder balls (35) mounted on the footprint of the component, Fig. 5.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use common adhesive such as solder in order to electrically connect the components to the circuit board.
Allowable Subject Matter
Claims 7, 12, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 5, a combination of limitations that a dip switch communicatively coupled to the first electronic component, wherein the first electronic component is configured to utilize the first communication protocol or the second communication protocol based on a setting of the dip switch. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1, 8, 10, a combination of limitations that the voltage divider comprises an impedance element and a conductive bridge configurable to short-circuit the impedance element, and the reference voltage is adjustable by short-circuiting the impedance element via the conductive bridge. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimizu (US 20150282323) discloses components mounted on the circuit board, Fig. 10.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2848