Prosecution Insights
Last updated: August 17, 2026
Application No. 18/593,833

A SEMICONDUCTOR DEVICE HAVING SEPARATION REGION CONTACTING GUARD RING REGION AND DEEP SEMICONDUCTOR REGION PARTITIONING A DEVICE PART INTO A PLURALITY OF DEVICE REGIONS AND THE SEPARATION REGION HAVING A WIDTH LESS THAN A WIDTH OF GUARD RING REGION

Final Rejection §102§112
Filed
Mar 01, 2024
Priority
Nov 08, 2019 — JP 2019-203060 +1 more
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
2 (Final)
38%
Grant Probability
At Risk
3-4
OA Rounds
1y 2m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
266 granted / 702 resolved
-30.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
32 currently pending
Career history
761
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
30.2%
-9.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 702 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Species 1, as shown in FIG. 9, was elected. Amendment filed April 24, 2026 is acknowledged. Claims 3 and 9-17 have been cancelled. Claims 1, 5 and 8 have been amended. Claims 1-2 and 4-8 are pending. Action on merits of the Elected Species, claims 1-2 and 4-8 follows. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 1-2 and 4-7 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There does not appear to be a written description of the claim limitations “wherein a current flowing in the second semiconductor region is smaller than a current flowing in the first semiconductor region” (amended claims 1); “wherein an analog circuit is formed in the second region” (claim 4); “a current flowing in the third semiconductor region and a current flowing in the fourth semiconductor region are smaller than a current flowing in the first semiconductor region and a current flowing in the second semiconductor region” (amended claim 5); “wherein analog circuits are formed respectively in the third region and the fourth region” (claim 6); and “wherein a width of the second guard ring region is less than a width of the first guard ring region” (claim 7) in the application as filed. The specification fails to support “a current flowing in the second semiconductor region (R2) is smaller than a current flowing in the first semiconductor region (R1)” (amended claim 1) or “a current flowing in the third semiconductor region (R3) and a current flowing in the fourth semiconductor region (R4) are smaller than a current flowing in the first semiconductor region (R1) and a current flowing in the second semiconductor region (R2)” (amended claim 5). Therefore, claims 1, 5 and all dependent claims contains unsupported, new matters. Claim 4 recites: “the semiconductor device according to claim 1, wherein an analog circuit is formed in the second region”. [0030] discloses: “The small current element 52 is a portion of a small current circuit handling a small current. The small current circuit is, for example, a signal processing circuit, e.g., an analog circuit”. Therefore, claim 4 contains unsupported, new matter. Claim 6 recites: “the semiconductor device according to claim 5, wherein analog circuits are formed respectively in the third region and the fourth region”. Similar to claim 4 above, claim 6 contains unsupported, new matter. Claim 7 recites: “the semiconductor device according to claim 5, wherein a width of the second guard ring region is less than a width of the first guard ring region”. The width of guard ring 19 surrounding the device parts (R1, R2, R3, R4) are the same. Therefore, claim 7 contains unsupported, new matter. Applicant must cancel the un-support new matters in response to the Office Action. Since claims 1-2 and 3-7 contain un-supported new matters, thus, action on merits of claims 1-2 and 4-7 are impossible, therefore, excluded. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 2 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 2 recites: The semiconductor device according to claim 1, wherein a width of the first separation region is less than a width of the first guard ring region. However, the same limitation had already been claimed in amended claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by SONE et al. (JP. Pub. No. 2014146833) of record. With respect to claim 1, SONE teaches a semiconductor device as claimed including: a semiconductor substrate (2) of a first conductivity type (p); a semiconductor layer (42d) provided on the semiconductor substrate, the semiconductor layer (42d) being of the first conductivity type (p); a first deep (42b) semiconductor region provided between the semiconductor substrate and the semiconductor layer (42d), the first deep (42b) semiconductor region being of a second conductivity type (n); a first guard ring region (42a) of the second conductivity type (n), the first guard ring region (42a) and the first deep (42b) semiconductor region surrounding a first device part (42) of the semiconductor layer (42d); a first separation region (42c, middle) contacting the first guard ring region (42a) and the first deep semiconductor region (42b), partitioning the first device part (42) into a first region (upper left) and a second region (upper right), and being of the second conductivity type (n); a first semiconductor region (42d, upper left) provided in the first region (upper left), the first semiconductor region (42d, upper left) being of the first conductivity type (p); and a second semiconductor region (42d, upper right) provided in the second region (upper right), the second semiconductor region (42d, upper right) being of the first conductivity type (p), wherein a width of the first separation region (42c, middle) is less than a width of the first guard ring region (42a); and a third semiconductor region (42d, lower left) of the first conductivity type; and the first separation region (42c, middle) partitioning the first device part (42) into the first region (upper left), the second region (upper right), a third region (lower left), the third semiconductor region (42d, lower left) being provided in the third region (lower left). (See FIGs. 19, 30, 33). PNG media_image1.png 302 378 media_image1.png Greyscale Response to Arguments Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 1 earlier event
Apr 16, 2024
Response after Non-Final Action
Sep 05, 2025
Non-Final Rejection mailed — §102, §112
Dec 04, 2025
Applicant Interview (Telephonic)
Dec 05, 2025
Response after Non-Final Action
Dec 05, 2025
Response Filed
Dec 08, 2025
Examiner Interview Summary
Apr 24, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
38%
Grant Probability
48%
With Interview (+10.0%)
3y 8m (~1y 2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 702 resolved cases by this examiner. Grant probability derived from career allowance rate.

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