DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed August 4th, 2026, in which: claims 1, 3-8, 10, 12-16, and 18-20 are amended; claims 2 and 11 are cancelled; and the rejection of the claims are traversed. Claims 1, 2-10, and 12-20 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-7, 10, 13-16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juengling (US 7391070 B2), in view of Furukawa (US 6221704 B1) and Jen (US 20210013104 A1).
Regarding independent claim 1, Juengling teaches a semiconductor memory device manufacturing method comprising: forming a gate structure on a substrate ([0065], “…first semiconductor material, oxide-containing material…”), forming a gate oxide material between adjacent ones of the first gate nitride spacers ([0077], “…dielectric material 42 is provided within the first portion 38 of openings 22…Dialectric material 42 can, for example, comprise…silicon dioxide.”), forming a first gate cap nitride layer over the gate structure, the first gate nitride spacers and the gate oxide material ([0085], “…material 52 is deposited within gaps 48, and over pillars 50…Material 52 can, for example, comprise…a nitride-containing material…”), patterning the first gate cap nitride layer and using the patterned first gate cap nitride layer as a hard mask to etch gate contact trenches in the gate oxide material, wherein each gate contact trench exposes a corresponding gate source/drain region in the substrate ([0087], “…patterned masking material 54 is provided over material 53. Masking material… can be patterned by photolithographic processing”, [[0089], “…gaps 58 are extended through materials 53 and 14, and subsequently masking layer 54…is removed.”), forming second gate nitride spacers in the gate contact trenches ([0091], “…material 62 is anisotropically etched to form spacers 64.”), forming a gate contact oxide material in the gate contact trenches and over the second gate nitride spacers ([0092], “…a dielectric material 66 is formed within the openings…Dielectric material 66 can comprise, for example, silicon dioxide…”), forming a second gate cap nitride layer over the gate structure, the first and second gate nitride spacers and the gate contact oxide material ([0090], “…material 62 is provided over lines 60…Material 62 can, for example, comprise… silicon nitride…”), patterning the second gate cap nitride layer to form an opening to expose the gate contact oxide material ([0100], “…masking material 84 is formed over regions 72 to protect the regions from subsequent processing…”), removing the gate contact oxide material from the gate contact trenches ([0101], “…material 14 is selectively removed relative to material 76…”), and forming a gate contact metal material into the gate contact trenches ([0102], “…semiconductor material 88 is formed within openings 86. Material 88 can be formed by, for example, forming polycrystalline silicon within openings…”).
However, Juengling does not teach wherein the gate structure comprises an oxide layer, a polysilicon portion in contact with the oxide layer, and a tungsten portion in contact with the polysilicon portion; forming first gate nitride spacers around the gate structure, wherein each first gate nitride spacer is in contact with lateral sidewalls of the oxide layer, the polysilicon portion, and the tungsten portion; and each oxide spacer is in contact with a corresponding one of the first gate nitride spacers; wherein each second gate nitride spacer is in contact with a corresponding one of the oxide spacers, each oxide spacer is sandwiched between a corresponding one of the first gate nitride spacers and a corresponding one of the second gate nitride spacers.
However, in the same field of endeavor, Furukawa teaches wherein the gate structure comprises an oxide layer (Fig. 3, 3, 4, 7; (Col. 3, Lines 36-37), "The first insulating layer 3 can be provided by thermal oxidation of silicon substrate…"), a polysilicon portion in contact with the oxide layer (Fig. 3, 3, 4, 7; (Col. 3, Lines 43-47), "The conductive material 4 does not have to be conductive when it is deposited but it must be made conductive at the end of the process. For instance, different ways exist to make it conductive. For example, a conductive material such as doped polysilicon can be deposited."), and a tungsten portion in contact with the polysilicon portion (Fig. 3, 3, 4, 7; (Col. 6, Lines 45-46), "Examples of suitable conductive material 7 include tungsten..."); forming first gate nitride spacers around the gate structure, wherein each first gate nitride spacer is in contact with lateral sidewalls of the oxide layer, the polysilicon portion, and the tungsten portion (Fig. 3, 9; (Col. 7, Line 14), "...with oxide or nitride spacer 9."); and Jen teaches each oxide spacer is in contact with a corresponding one of the first gate nitride spacers; wherein each second gate nitride spacer is in contact with a corresponding one of the oxide spacers, each oxide spacer is sandwiched between a corresponding one of the first gate nitride spacers and a corresponding one of the second gate nitride spacers (Fig. 7, 116, 118, 120; [0025], "...the second nitride spacer 120, the first oxide spacer 118, the first nitride spacer 116…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Juengling with the gate structure of Furukawa so as to manufacture a "higher performance MOSFET", (Furukawa, Col. 1, Line 27), and with the spacers of Jen so as "to overcome problems caused by scaling down the elements", (Jen, [0003]).
Regarding dependent claim 4, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, and further teaches performing a chemical mechanical polishing process to remove excess gate oxide material ([0121], “…an upper surface…is planarized to remove materials 106 and 98…The planarization can be accomplished by, for example, chemical-mechanical polishing…The materials 106 and 98…can both be silicon dioxide.”).
Regarding dependent claim 5, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, and further teaches performing a chemical mechanical polishing process to remove excess gate contact oxide material ([0121], “…an upper surface…is planarized to remove materials 106 and 98…The planarization can be accomplished by, for example, chemical-mechanical polishing…The materials 106 and 98…can both be silicon dioxide.”).
Regarding dependent claim 6, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, and further teaches performing a chemical mechanical polishing process to remove excess gate contact metal material ([0082], “…material 47 can consist essentially of silicon nitride…”, [0083], “…subjected to planarization (such as, for example, chemical-mechanical polishing) to planarize an upper surface of the construction. Such planarization removed material 47…”).
Regarding dependent claim 7, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, wherein an inner sidewall of each gate contact trench is perpendicular to the corresponding gate source/drain region (Fig. 113, #88 source/drain region, #132, perpendicular sidewalls).
Regarding dependent claim 10, Juengling teaches a semiconductor memory device manufacturing method comprising: forming a gate structure on a substrate ([0063], “…further comprises a material 14 over substrate 12.”), forming a gate oxide material between adjacent ones of the first gate nitride spacers (([0077], “…dielectric material 42 is provided within the first portion 38 of openings 22…Dialectric material 42 can, for example, comprise…silicon dioxide.”), forming a first gate cap nitride layer over the gate structure, the first gate nitride spacers and the gate oxide material ([0085], “…material 52 is deposited within gaps 48, and over pillars 50…Material 52 can, for example, comprise…a nitride-containing material…”), patterning the first gate cap nitride layer and using the patterned first gate cap nitride layer as a hard mask to etch gate contact trenches in the gate oxide material, wherein each gate contact trench has a first opening having a first width ([0087], “…patterned masking material 54 is provided over material 53. Masking material… can be patterned by photolithographic processing”, [[0089], “…gaps 58 are extended through materials 53 and 14, and subsequently masking layer 54…is removed.”), forming second gate nitride spacers in the gate contact trenches ([0091], “…material 62 is anisotropically etched to form spacers 64.”), forming a gate contact oxide material in the gate contact trenches and over the second gate nitride spacers ([0092], “…a dielectric material 66 is formed within the openings…Dielectric material 66 can comprise, for example, silicon dioxide…”), forming a second gate cap nitride layer over the gate structure, the first and second gate nitride spacers and the gate contact oxide material ([0090], “…material 62 is provided over lines 60…Material 62 can, for example, comprise… silicon nitride…”), patterning the second gate cap nitride layer to form a second opening to expose the gate contact oxide material, wherein the second opening has a second with greater than the first width ([0100], “…masking material 84 is formed over regions 72 to protect the regions from subsequent processing…”), removing the gate contact oxide material from the gate contact trenches ([0101], “…material 14 is selectively removed relative to material 76…”), and forming a gate contact metal material into the gate contact trenches to form gate contacts ([0102], “…semiconductor material 88 is formed within openings 86. Material 88 can be formed by, for example, forming polycrystalline silicon within openings…”).
However, Juengling does not teach wherein the gate structure comprises an oxide layer, a polysilicon portion in contact with the oxide layer, and a tungsten portion in contact with the polysilicon portion; forming first gate nitride spacers around the gate structure, wherein each first gate nitride spacer is in contact with lateral sidewalls of the oxide layer, the polysilicon portion, and the tungsten portion; and each oxide spacer is in contact with a corresponding one of the first gate nitride spacers; wherein each second gate nitride spacer is in contact with a corresponding one of the oxide spacers, each oxide spacer is sandwiched between a corresponding one of the first gate nitride spacers and a corresponding one of the second gate nitride spacers.
However, in the same field of endeavor, Furukawa teaches wherein the gate structure comprises an oxide layer (Fig. 3, 3, 4, 7; (Col. 3, Lines 36-37), "The first insulating layer 3 can be provided by thermal oxidation of silicon substrate…"), a polysilicon portion in contact with the oxide layer (Fig. 3, 3, 4, 7; (Col. 3, Lines 43-47), "The conductive material 4 does not have to be conductive when it is deposited but it must be made conductive at the end of the process. For instance, different ways exist to make it conductive. For example, a conductive material such as doped polysilicon can be deposited."), and a tungsten portion in contact with the polysilicon portion (Fig. 3, 3, 4, 7; (Col. 6, Lines 45-46), "Examples of suitable conductive material 7 include tungsten..."); forming first gate nitride spacers around the gate structure, wherein each first gate nitride spacer is in contact with lateral sidewalls of the oxide layer, the polysilicon portion, and the tungsten portion (Fig. 3, 9; (Col. 7, Line 14), "...with oxide or nitride spacer 9."); and Jen teaches each oxide spacer is in contact with a corresponding one of the first gate nitride spacers; wherein each second gate nitride spacer is in contact with a corresponding one of the oxide spacers, each oxide spacer is sandwiched between a corresponding one of the first gate nitride spacers and a corresponding one of the second gate nitride spacers (Fig. 7, 116, 118, 120; [0025], "...the second nitride spacer 120, the first oxide spacer 118, the first nitride spacer 116…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Juengling with the gate structure of Furukawa so as to manufacture a "higher performance MOSFET", (Furukawa, Col. 1, Line 27), and with the spacers of Jen so as "to overcome problems caused by scaling down the elements", (Jen, [0003]).
Regarding dependent claim 13, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, and further teaches performing a chemical mechanical polishing process to remove excess gate oxide material ([0121], “…an upper surface…is planarized to remove materials 106 and 98…The planarization can be accomplished by, for example, chemical-mechanical polishing…The materials 106 and 98…can both be silicon dioxide.”).
Regarding dependent claim 14, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, and further teaches performing a chemical mechanical polishing process to remove excess gate contact oxide material ([0121], “…an upper surface…is planarized to remove materials 106 and 98…The planarization can be accomplished by, for example, chemical-mechanical polishing…The materials 106 and 98…can both be silicon dioxide.”).
Regarding dependent claim 15, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, and further teaches performing a chemical mechanical polishing process to remove excess gate contact metal material ([0082], “…material 47 can consist essentially of silicon nitride…”, [0083], “…subjected to planarization (such as, for example, chemical-mechanical polishing) to planarize an upper surface of the construction. Such planarization removed material 47…”).
Regarding dependent claim 16, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, wherein each gate contact comprises a T-shaped profile (Fig. 122, #146; [0137], “…an electrically conductive material 146 is formed within gaps 142.”)
Regarding dependent claim 18, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, wherein each gate contact trench exposes a corresponding gate source/drain region in the substrate ([0104], “…the semiconductor material 88 within openings 86 can ultimately correspond to source/drain regions…”).
Regarding dependent claim 20, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 18, wherein each second gate nitride spacer has a uniform thickness and extends in a lengthwise direction perpendicular to the corresponding gate source/drain region (Fig. 113, #88 source/drain region, #132, perpendicular sidewalls).
Claim(s) 3, 8, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juengling (US 7391070 B2) in further view of Furukawa (US 6221704 B1), Jen (US 20210013104 A1), and Lin (US 20240120399 A1).
Regarding dependent claim 3, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, but does not teach that the gate contact metal material comprises tungsten.
However, in the same field of endeavor, Lin teaches that the gate contact metal material comprises tungsten (Paragraph [0038].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacturing taught by Juengling with the tungsten gate contact of Lin in order to “reduce contact resistance” (Lin, [0038]).
Regarding dependent claim 8, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, but does not teach performing a source/drain implant process to the corresponding gate source/drain region.
However, in the same field of endeavor, Lin teaches performing a source/drain implant process to the corresponding gate source/drain region (Paragraph [0043].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacture taught by Juengling with the source/drain implement process of Lin in order to “dope the source/drain features” without in-situ doping (Lin, [0043]).
Regarding dependent claim 12, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, but does not teach that the gate contact metal material comprises tungsten.
However, in the same field of endeavor, Lin teaches that the gate contact metal material comprises tungsten (Paragraph [0038].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacturing taught by Juengling with the tungsten gate contact of Lin in order to “reduce contact resistance” (Lin, [0038]).
Regarding dependent claim 19, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 18, but does not teach performing a source/drain implant process to the corresponding gate source/drain region.
However, in the same field of endeavor, Lin teaches performing a source/drain implant process to the corresponding gate source/drain region (Paragraph [0043].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacture taught by Juengling with the source/drain implement process of Lin in order to “dope the source/drain features” without in-situ doping (Lin, [0043]).
Claim(s) 9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juengling (US 7391070 B2) in further view of Furukawa (US 6221704 B1), Jen (US 20210013104 A1), and Yi (US 20180366478 A1).
Regarding dependent claim 9, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 1, but does not teach that the second gate nitride spacers are formed by an atomic layer deposition process.
However, in the same field of endeavor, Yi teaches that the spacers are formed by an atomic layer deposition process ([0015] defines deposition, [0016] includes ALD as a method of deposition, [0022] teaches the deposition of spacers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacture of Juengling with the ALD process of Yi so as to apply the material to the substrate in a “suitable known matter” (Yi, [0015], [0016]).
Regarding dependent claim 17, Juengling, as previously modified by Furukawa and Jen, teaches the method of claim 10, but does not teach that the second gate nitride spacers are formed by an atomic layer deposition process.
However, in the same field of endeavor, Yi teaches that the spacers are formed by an atomic layer deposition process ([0015] defines deposition, [0016] includes ALD as a method of deposition, [0022] teaches the deposition of spacers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacture of Juengling with the ALD process of Yi so as to apply the material to the substrate in a “suitable known matter” (Yi, [0015], [0016]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20190097027 A1, pertaining to a method of manufacturing a memory cell involving deposition on a substrate, as well as gate structures and the use of polysilicon.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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