Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20220122982 A1), in view of Lu (US 20220310619 A1).
Regarding independent claim 1, Shih teaches a memory device, comprising: a capacitor contact structure (Fig. 41, 401; [0087], "...capacitor contact structures 401 may be formed in the capacitor contact openings 703."), a bit line structure disposed on the semiconductor substrate and adjacent to the capacitor contact structure (Fig. 41, 101, 301; [0075], "...bit line structures 301 and bit line spacers 313 may be formed on the substrate 101."); and a spacer structure between the bit line structure and the capacitor contact structure (Fig. 41, 313; [0080], "...concurrently form the bit line spacers 313 attached on sidewalls of the bit line structures 301.").
However, Shih does not teach wherein the capacitor extends from a top surface of the capacitor contact structure to a sidewall of the capacitor contact structure.
However, in the same field of endeavor, Lu teaches wherein the capacitor extends from a top surface of the capacitor contact structure to a sidewall of the capacitor contact structure (Fig. 25, 107, 302; [0079], "...may allow each of the conductive blocks 302 to correspond to one of the capacitor connection holes 106 and cause each of the conductive blocks 302 to be connected to the capacitor contact structure 107 that corresponds to the capacitor connection hole 106.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device of Shih with the capacitor of Lu so that the capacitor can "be bonded to the capacitor contact structure", (Lu, [0076]).
Regarding dependent claim 2, Shih, as previously modified by Lu, teaches the memory device of claim 1, and further teaches wherein the spacer structure comprises a first spacer along a sidewall of the bit line structure and a second spacer along a sidewall of the capacitor contact structure (Fig. 41, 313, (All spacers are labeled 313 and are adjacent to the capacitor contact structure and bit line structure)).
Regarding dependent claim 4, Shih, as previously modified by Lu, teaches the memory device of claim 2, and further teaches wherein the first spacer further extends to the sidewall of the capacitor contact structure (Fig. 41, 313, 401, (This is self-explanatory from the diagram)).
Regarding dependent claim 7, Shih, as previously modified by Lu, teaches the memory device of claim 1, and further teaches wherein the spacer structure extends to a top surface of the capacitor contact structure (Fig. 41, 313, 401, (The top surfaces of the contact structure and spacer are coplanar)).
Regarding dependent claim 8, Shih, as previously modified by Lu, teaches the memory device of claim 1. However, as previously combined, they do not teach wherein a bottom surface of the capacitor is in contact with the spacer structure.
However, Lu further teaches wherein a bottom surface of the capacitor is in contact with the spacer structure (Fig. 25, (The spacer next to the contact structure 107 is not labeled, but is mentioned in [0047], "In the manufacturing process, an insulating structure is firstly formed on a substrate, and the insulating structure has a plurality of holes extending to the substrate, then a conductive material is deposited in each of the plurality of holes so as to form the each of the plurality of capacitor connection lines in the hole.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the bottom surface of the capacitor of Lu so that the capacitor can "be bonded to the capacitor contact structure", (Lu, [0076]).
Regarding dependent claim 9, Shih, as previously modified by Lu, teaches the memory device of claim 1, and further teaches wherein the bit line structure further comprises a bit line and a cap layer over the bit line (Fig. 41, 303, 305, 307, 309; [077], "...a series of deposition processes may be sequentially performed to deposit a bit line bottom conductive layer 303, a bit line middle conductive layer 305, a bit line top conductive layer 307, and a bit line capping layer 309...").
However, as previously combined, they do not teach and the capacitor is in contact with the cap layer.
However, Lu further teaches and the capacitor is in contact with the cap layer (Fig. 27, 50, 302; [0082], "...a conductive capping layer 50 is formed on a top wall and sidewalls of each of the plurality of conductive blocks 302…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the capacitor in contact with the cap layer of Lu for "improving the performance of the semiconductor structure", (Lu, [0083]).
Regarding dependent claim 10, Shih, as previously modified by Lu, teaches the memory device of claim 9. However, as previously combined, they do not teach wherein a bottom surface of the capacitor is lower than a top surface of the cap layer.
However, Lu further teaches herein a bottom surface of the capacitor is lower than a top surface of the cap layer (Fig. 27, 50, 302).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the bottom surface of the capacitor of Lu for "improving the performance of the semiconductor structure", (Lu, [0083]).
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20220122982 A1), in view of Lu (US 20220310619 A1) and Tung (US 20230008188 A1).
Regarding dependent claim 3, Shih, as previously modified by Lu, teaches the memory device of claim 2. However, as previously combined, they do not teach wherein the first spacer and the second spacer are made of different materials.
However, in the same field of endeavor, Tung teaches wherein the first spacer and the second spacer are made of different materials ([0018], "...the first spacer and the second spacer may contain different dielectric materials.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the different materials of Tung so that "the electrical isolation effect can be improved", (Tung, [0005]).
Regarding dependent claim 5, Shih, as previously modified by Lu, teaches the memory device of claim 4. However, as previously combined, they do not teach wherein the first spacer is in contact with a top surface of the second spacer.
However, in the same field of endeavor, Tung teaches wherein the first spacer is in contact with a top surface of the second spacer ([0018], "...or a composite layer structure, for example, including a first spacer and a second spacer formed in sequence…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the stacked spacers of Tung so that "the electrical isolation effect can be improved", (Tung, [0005]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20220122982 A1), in view of Lu (US 20220310619 A1), Tung (US 20230008188 A1), and Yan (US 20230422480 A1).
Regarding dependent claim 6, Shih, as previously modified by Lu and Tung, teaches the memory device of claim 5. However, as previously combined, they do not teach wherein the capacitor contact structure comprises a lower contact plug and an upper contact plug over the lower contact plug, and wherein the top surface of the second spacer is lower than a top surface of the lower contact plug.
However, in the same field of endeavor, Yan teaches wherein the capacitor contact structure comprises a lower contact plug and an upper contact plug over the lower contact plug (Fig. 50, 152, 1524, 1525; [0128], "...the barrier layer 1524 and the third conductive layer 1525 constitute the conductive plug 152…"), and wherein the top surface of the second spacer is lower than a top surface of the lower contact plug (Fig. 50, 152, 50; [0085], "...forming a protective layer 50 on a side wall…", (The top surface of this spacing element is lower than that of the plug)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih, Lu, and Yan with the contact plug layout of Yan so as to "prevent the conductive material in th conductive layer from diffusing into the insulating layer", (Yan, [0130]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20220122982 A1), in view of Lu (US 20220310619 A1) and Yeem (US 20240280895 A1).
Regarding dependent claim 11, Shih, as previously modified by Lu, teaches the memory device of claim 1, and further teaches wherein the bit line structure further comprises a bit line and a cap layer over the bit line (Fig. 41, 303, 305, 307, 309; [077], "...a series of deposition processes may be sequentially performed to deposit a bit line bottom conductive layer 303, a bit line middle conductive layer 305, a bit line top conductive layer 307, and a bit line capping layer 309...").
However, as previously combined, they do not teach and the spacer structure is in contact with a top surface of the cap layer.
However, in the same field of endeavor, Yeem teaches the spacer structure is in contact with a top surface of the cap layer (Fig. 10B, 167, 166; [0082], "The bit line spacer 167 may cover top and side surfaces of the bit line capping layer 166…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory device as described by the combination of Shih and Lu with the spacer structure contact of Yeem so as to "improve the electrical characteristics of semiconductor devices" (Yeem, [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230031883 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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