DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17, in the reply filed on 07/20/2026 is acknowledged. Claims 18-20 are therefore withdrawn.
Status of the Application
Claims 1-20 remain pending in this application. Claims 18-20 are withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it recites the limitation “each of the ferroelectric films has a thickness in the first direction that is greater than the electrode layer that is in contact therewith” in lines 7 and 8, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. Specifically, the limitation compares a thickness of each of the ferroelectric films to the electrode layer itself, rather than to another dimension. For example, it is unclear if the claim is intended to require a thickness of each of the ferroelectric films to be greater than a thickness of the one of the electrode layers that is in contact with in the first direction, greater than a width of the one of the electrode layers that is in contact with in a second direction, or some other meaning. This renders the scope of the claim indefinite. For the purposes of compact prosecution, the examiner is interpreting the limitation to have intended to state “is greater than a thickness in the first direction of the one of the electrode layers that is in contact therewith”.
Regarding claims 2-12, the claims depend from rejected claim 1, includes all limitations of claim 1 and are therefore rejected for the same reason. The claims will be examined on the basis of interpretation of the rejected claim hereafter.
Regarding claim 2, it recites the limitation “the flat direction” in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the first direction”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 13, it recites the limitation “the ferroelectric film of each of the ferroelectric memory cells has a thickness in the first direction that is greater than the electrode layer that is in contact therewith” in lines 12 and 13, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. Specifically, the limitation compares a thickness of each of the ferroelectric films to the electrode layer itself, rather than to another dimension. For example, it is unclear if the claim is intended to require a thickness of each of the ferroelectric films to be greater than a thickness of an electrode layer that is in contact with in the first direction, greater than a width of an electrode layer that is in contact with in a second direction, or some other meaning. This renders the scope of the claim indefinite.
Further, it recites the limitation “the electrode layer that is in contact therewith” in line 13. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “one of the electrode layers that is in contact therewith”, in which case proper antecedent basis is established.
For the purposes of compact prosecution, the examiner is interpreting the limitation to have intended to state “is greater than a thickness in the first direction of one of the electrode layers that is in contact therewith”.
Regarding claims 14-17, the claims depend from rejected claim 13, includes all limitations of claim 13 and are therefore rejected for the same reason. The claims will be examined on the basis of interpretation of the rejected claim hereafter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 20210036019 A1, hereafter Sharangpani) in view of Lue (US 20210074726 A1, hereafter Lue).
Regarding claim 1, Sharangpani teaches: A semiconductor memory device (Sharangpani fig 11A, ¶0006), comprising:
a stacked body (Sharangpani 32, 46, ¶0006) in which a plurality of electrode layers (Sharangpani 46, ¶0132-0134) and a plurality of insulating layers (Sharangpani 32, ¶0088) are alternately stacked in a first direction (Sharangpani fig 11A, vertical with respect to fig 11A)(Sharangpani fig 11A, ¶0088);
a pillar (Sharangpani 160, ¶0107-0109) that extends in the stacked body in the first direction (Sharangpani fig 11A, ¶0108); and
a plurality of ferroelectric films (Sharangpani 44E, 44P, ¶0126-0128, 0183), each of which is disposed between and in contact with one of the electrode layers and the pillar (Sharangpani fig 10C, 10D, 11A, ¶0126, 0128, 0132), wherein
each of the ferroelectric films has a thickness in the first direction that is greater than the electrode layer that is in contact therewith (as best understood to mean “is greater than a thickness in the first direction of the one of the electrode layers that is in contact therewith”)(Sharangpani fig 10A-D, 11A, ¶0123-0124, 0132, at least 44E has a thickness in the vertical direction that is greater than a thickness of 46 which fills 43 after 44E and 44P are formed within 43).
Sharangpani does not explicitly teach: the pillar having an electrode film; and
the plurality of ferroelectric films, each of which is disposed between and in contact with one of the electrode layers and the electrode film.
Lue, in the same field of endeavor of semiconductor device manufacturing, teaches: a pillar (Lue 308, 310, 312 ¶0059) having an electrode film (Lue 308, ¶0058, applicant discloses that an “electrode film corresponds to a channel region”, spec ¶0047 and “semiconductor film CH functions as a channel region”, spec ¶0075) that extends in a stacked body (Lue 302, ¶0057) in a first direction (Lue fig 3, vertical with respect to fig 3); and
a plurality of ferroelectric films (Lue 308, ¶0058), each of which is disposed between and in contact with one of a plurality of electrode layers (Lue 304, ¶0057) and the electrode film (Lue fig 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the pillar of Sharangpani with the pillar of Lue, such that it comprised an electrode film, and such that “a plurality of ferroelectric films, each of which is disposed between and in contact with one of the electrode layers and the electrode film”, as taught by Lue, in order to reduce pitch, thereby reducing device size (Lue ¶0005, 0050-0051).
Regarding claim 2, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 1, wherein a side face of each of the ferroelectric films (Sharangpani 44E, 44P) in contact with the corresponding electrode layer (Sharangpani 46) is flat in the flat direction (as best understood to mean “the first direction”)(Sharangpani fig 11A, vertical with respect to fig 11A)(Sharangpani fig 10D, 11A, ¶0126, at least 44E and 46 share an interface oriented in the first direction that is flat).
Regarding claim 3, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 2, wherein a side face of each of ferroelectric films (Sharangpani 44E, 44P) in contact with the electrode film (Lue 308, Sharangpani as modified by Lue) is flat in the first direction (Sharangpani fig 11A, vertical with respect to fig 11A, similar to Lue vertical with respect to fig 3)(Sharangpani fig 10D, 11A, ¶0126, at least 44E and 160 share an interface oriented in the first direction that is flat, similar to Lue fig 4, 308).
Regarding claim 4, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 1, wherein the electrode film (Lue 308, Sharangpani as modified by Lue) is an undoped semiconductor film (Lue ¶0087, 0111, “undoped polysilicon layer”), and the electrode layer (Sharangpani 46) is a conductive layer (Sharangpani ¶0080, 0132, “electrically conductive layers”).
Regarding claim 7, Sharangpani in view of Lue, in at least one embodiment, teaches: The semiconductor memory device according to claim 1, wherein
each of the ferroelectric films (Sharangpani 44E, 44P) includes a plurality of crystals (Sharangpani ¶0126-0128, textured 44E and 44P), each having a polarizing axis (Sharangpani ¶0124, “spontaneous electrical polarization”), and in an initial state thereof, has a smaller percentage of the crystals that have polarizing axes that are generally aligned with a direction from the electrode layer (Sharangpani 46) toward the electrode film (Lue 308, Sharangpani as modified by Lue)(Sharangpani fig 10D, horizontal with respect to fig 10D) than those that are generally perpendicular to the direction (Sharangpani ¶0128, in at least one embodiment more than 50% are vertically aligned with 160, therefore the percentage that are generally aligned is less than a percentage that are not aligned to the horizontal direction).
Regarding claim 9, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 1, wherein the ferroelectric films (Sharangpani 44E, 44P) are formed of a material having hafnium oxide as a main component (Sharangpani ¶0125, 0129, 0183).
Regarding claim 10, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 9, wherein the ferroelectric films (Sharangpani 44E, 44P) are formed of a material further including at least one element selected from a group including silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)(Sharangpani ¶0125, 0129, “doped with at least one of Si, Y, Gd, La, Sr, Zr or Al”).
Regarding claim 11, Sharangpani in view of Lue, in at least one embodiment, teaches: The semiconductor memory device according to claim 1, wherein an outer side face of the electrode film (Sharangpani 160 as modified by Lue 308) has a plurality of protruding portions at locations corresponding to the plurality of ferroelectric films (Sharangpani 44E, 44P)(Sharangpani fig 6A-C, 10F, ¶0114, 0136, outer portions of 160 protrude between 32).
Regarding claim 12, Sharangpani in view of Lue, in at least one embodiment, teaches: The semiconductor memory device according to claim 1, wherein an outer side face of the electrode film (Sharangpani 160 as modified by Lue 308) has a plurality of recessed portions corresponding to the plurality of ferroelectric films (Sharangpani 44E, 44P)(Sharangpani fig A29A, ¶0210, outer portions of 160 is recessed between 32).
Regarding claim 13, Sharangpani teaches: A semiconductor memory device (Sharangpani fig 10D, 10F, 11A, ¶0006, 0079), comprising:
a stacked body (Sharangpani 32, 46, ¶0006) in which a plurality of electrode layers (Sharangpani 46, ¶0132-0134) and a plurality of insulating layers (Sharangpani 32, ¶0088) are alternately stacked in a first direction (Sharangpani fig 11A, vertical with respect to fig 11A)(Sharangpani fig 11A, ¶0088);
a pillar (Sharangpani 160, ¶0107-0109) that extends in the stacked body in the first direction (Sharangpani fig 11A, ¶0108); and
a plurality of ferroelectric memory cells (Sharangpani “ferroelectric memory elements“, ¶0073, 0122, as best shown by 46 in fig 10A-H and 11A) at intersections of the pillar and the electrode layers (Sharangpani fig 10D, 11A, ¶0128, 0134, one at each level of 46 around 160), each of the ferroelectric memory cells including a semiconductor channel (Sharangpani 160, fig 10F, ¶0111, 0136, portion at each level), a conductive layer (Sharangpani 46, ¶0134, portion at each level), and a ferroelectric film (Sharangpani 44E, 44P, ¶0126-0128, 0183, formed in each 43) between and in contact with the semiconductor channel and the conductive layer (Sharangpani fig 10D, 10F, 11A), wherein one of the semiconductor channel and the conductive layer is formed from a part of the pillar and the other one of the semiconductor channel and the conductive layer is formed from a part of the electrode layers (Sharangpani fig 10D, 10F, 11A, ¶0126-0128, 0134, 0181-0183), wherein
the ferroelectric film of each of the ferroelectric memory cells has a thickness in the first direction that is greater than the electrode layer that is in contact therewith (as best understood to mean “is greater than a thickness in the first direction of one of the electrode layers that is in contact therewith”)(Sharangpani fig 10A-F, 11A, ¶0123-0124, 0132, at least 44E has a thickness in the vertical direction that is greater than a thickness of 46 which fills 43 after 44E and 44P are formed within 43).
Sharangpani does not explicitly teach: the pillar having an electrode film on an outer periphery thereof; and
the plurality of ferroelectric memory cells are at intersections of the electrode film and the electrode layers, wherein one of the semiconductor channel and the conductive layer is formed from a part of the electrode film.
Lue, in the same field of endeavor of semiconductor device manufacturing, teaches: a pillar (Lue 308, 310, 312 ¶0059) having an electrode film (Lue 308, ¶0058, applicant discloses that an “electrode film corresponds to a channel region”, spec ¶0047 and “semiconductor film CH functions as a channel region”, spec ¶0075) on an outer periphery thereof that extends in a stacked body (Lue 302, ¶0057) in a first direction (Lue fig 3, vertical with respect to fig 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the pillar of Sharangpani with the pillar of Lue, such that “a pillar having an electrode film on an outer periphery thereof that extends in the stacked body in the first direction”, as taught by Lue, and such that “a plurality of ferroelectric memory cells at intersections of the electrode film and the electrode layers, wherein one of the semiconductor channel and the conductive layer is formed from a part of the electrode film”, in order to reduce pitch, thereby reducing device size (Lue ¶0005, 0050-0051).
Regarding claim 14, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 13, wherein the ferroelectric film (Sharangpani 44E, 44P) in each of the ferroelectric memory cells (Sharangpani “ferroelectric memory elements“, ¶0073, 0122, as best shown by 46 in fig 10A-H and 11A) has a first surface in contact with the semiconductor channel (Sharangpani 160) that is flat in the first direction (Sharangpani fig 11A, vertical with respect to fig 11A)(Sharangpani fig 10D, 11A, ¶0126, 44E and 160 share an interface oriented in the first direction that is flat) and a second surface in contact with the conductive layer (Sharangpani 46) that is flat in the first direction (44E and 46 share an interface oriented in the first direction that is flat).
Regarding claim 15, Sharangpani in view of Lue, in at least one embodiment, teaches: The semiconductor memory device according to claim 13, wherein an outer side face of the electrode film (Sharangpani 160 as modified by Lue 308) has a plurality of protruding portions at locations corresponding to the plurality of ferroelectric memory cells (Sharangpani “ferroelectric memory elements“, ¶0073, 0122, as best shown by 46 in fig 10A-H and 11A)(Sharangpani fig 6A-C, 10F, ¶0114, 0136, outer portions of 160 protrude between 32).
Regarding claim 16, Sharangpani in view of Lue, in at least one embodiment, teaches: The semiconductor memory device according to claim 13, wherein an outer side face of the electrode film (Sharangpani 160 as modified by Lue 308) has a plurality of recessed portions corresponding to the plurality of ferroelectric memory cells (Sharangpani “ferroelectric memory elements“, ¶0073, 0122, as best shown by 46 in fig 10A-H and 11A)(Sharangpani fig A29A, ¶0210, outer portions of 160 is recessed between 32).
Claims 6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 20210036019 A1, hereafter Sharangpani) in view of Lue et al (US 20210074726 A1, hereafter Lue), as applied to claim 1 or 13 above, and further in view of Ino et al (US 20190296122 A1, hereafter Ino).
Regarding claim 6, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 1.
Sharangpani in view of Lue does not explicitly teach: wherein each of the ferroelectric films exhibits antiferroelectricity in an initial state.
Ino, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a ferroelectric region (Ino 31-33, 61-63, ¶0109-0114) in a ferroelectric memory cell (Ino MT, ¶0096, 0132) exhibits antiferroelectricity (Ino ¶0031, 0113, 0198) in an initial state (Ino states that any of the regions are “one of the ferroelectric, the ferrielectric, or the anti-ferroelectric”, ¶0113, 0198, therefore in at least one embodiment, at least one of the permutations must be suitable as a material that “exhibits antiferroelectricity in an initial state”, also see MPEP 2112.01).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the ferroelectric films of Sharangpani in view of Lue such that it “exhibits antiferroelectricity in an initial state” in order to tailor the polarization behavior of the memory cells for a desired memory operation (Ino ¶0198).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an antiferroelectric material for the ferroelectric films of Sharangpani in view of Lue, which is known and commonly used in ferroelectric memory devices, and that use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Regarding claim 17, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 13.
Sharangpani in view of Lue does not explicitly teach: wherein the ferroelectric film in each of the ferroelectric memory cells exhibits antiferroelectricity in an initial state.
Ino, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a ferroelectric region (Ino 31-33, 61-63, ¶0109-0114) in a ferroelectric memory cell (Ino MT, ¶0096, 0132) exhibits antiferroelectricity (Ino ¶0031, 0113, 0198) in an initial state (Ino states that any of the regions are “one of the ferroelectric, the ferrielectric, or the anti-ferroelectric”, ¶0113, 0198, therefore in at least one embodiment, at least one of the permutations must be suitable as a material that “exhibits antiferroelectricity in an initial state”, also see MPEP 2112.01).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the ferroelectric film of Sharangpani in view of Lue such that it “exhibits antiferroelectricity in an initial state” in order to tailor the polarization behavior of the memory cells for a desired memory operation (Ino ¶0198).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an antiferroelectric material in the memory cells of Sharangpani in view of Lue, which is known and commonly used in ferroelectric memory devices, and that use of conventional materials to perform their known function is prima-facie obvious (See MPEP 2144.07).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al (US 20210036019 A1, hereafter Sharangpani) in view of Lue et al (US 20210074726 A1, hereafter Lue), as applied to claim 7 above, and further in view of Ino et al (US 20160005961 A1, hereafter Ino-961).
Regarding claim 8, Sharangpani in view of Lue teaches: The semiconductor memory device according to claim 7.
Sharangpani in view of Lue does not teach: wherein each of the crystals has a first crystal axis, a second crystal axis that is shorter than the first crystal axis, and a third crystal axis that is shorter than the first crystal axis and longer than the second crystal axis and functions as the polarizing axis.
Ino-961, in the same field of endeavor of semiconductor device manufacturing, teaches: a crystal (Ino-961 30, ¶0087) has a first crystal axis (Ino-961 a axis, ¶0087), a second crystal axis (Ino-961 a axis, ¶0087) that is shorter than the first crystal axis (Ino-961 ¶0087, “longest axis is b axis”, “shortest axis is a axis”), and a third crystal axis (Ino-961 c axis, ¶0087) that is shorter than the first crystal axis and longer than the second crystal axis and functions as the polarizing axis (Ino-961 ¶0087-0089).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the ferroelectric films of Sharangpani in view of Lue such that “each of the crystals has a first crystal axis, a second crystal axis that is shorter than the first crystal axis, and a third crystal axis that is shorter than the first crystal axis and longer than the second crystal axis and functions as the polarizing axis”, as taught by Ino-961, in order to reduce a coercive electric field by enhancing symmetry of a crystal, thereby reducing write and/or erase voltages (Ino-961 ¶0064, 0088).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimomura et al (US 20200286901 A1, hereafter Shimomura).
Regarding claim 1, Shimomura discloses: A semiconductor memory device (Shimomura fig 14C, 24A, 24B, ¶0132, 0142), comprising:
a stacked body (Shimomura 16, 70, fig 24A, ¶0123, 0132) in which a plurality of electrode layers (Shimomura 16, ¶0113-0114, 0122, under a BRI of “electrode layer”) and a plurality of insulating layers (Shimomura 24, ¶0123) are alternately stacked in a first direction (Shimomura ¶0123, 0132, fig 24A, vertically with respect to fig 24A);
an electrode film (Shimomura 62, 62F, ¶0132) that extends in the stacked body in the first direction (Shimomura ¶0115, “vertically-extending”, fig 14C, 15B); and
a plurality of ferroelectric films (Shimomura 60, ¶0113, 0142), each of which is disposed between and in contact with one of the electrode layers and the electrode film (Shimomura fig 14C, 24A), wherein
each of the ferroelectric films has a thickness in the first direction that is greater than the electrode layer that is in contact therewith (as best understood to mean “is greater than a thickness in the first direction of the one of the electrode layers that is in contact therewith”)(Shimomura fig 14C, ¶0111, 0119-0122, 0143, 60 surrounds 11, therefore 60 must have a greater total thickness than 11, were 11 becomes 16).
Regarding claim 5, Shimomura discloses: The semiconductor memory device according to claim 1, wherein the electrode film (Shimomura 62, 62F) is a conductive film (Shimomura ¶0114), and the electrode layer (Shimomura 16) is an undoped semiconductor layer (Shimomura ¶0003, 0122, 0132, “undoped (i.e. not intentionally doped)”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al (US 9941299 B1) is cited as an example of an analogous device further a ferroelectric material liner in a stacked body.
Yamaguchi et al (US 20190088870 A1) is cited as an example of an analogous device further a disclosing ferroelectric material crystal polarization relative to an electrode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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