CTNF 18/593,988 CTNF 98846 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Application Claims 1-20 remain pending in this application. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 Claims 7 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 7 , it recites the limitation "the second direction" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner interprets the claim to have intended to state “ a second direction”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Regarding claim 18 , it recites the limitation "the second direction" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner interprets the claim to have intended to state “ a second direction”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, and 9-11 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Gawase et al (US 20220302320 A1, foreign priority to JP 2021044169 A, published 17 Mar 2021, hereafter Gawase) . Regarding claim 1, Gawase discloses: A semiconductor device (Gawase MC 1, 210, fig 17, 19, 21) comprising: a semiconductor substrate (Gawase 250, ¶0145); a memory capacitor (Gawase 201, ¶0167) provided on the semiconductor substrate (Gawase fig 19); a first conductor (Gawase 22, ¶0133) provided above the memory capacitor and extending in a first direction (Gawase “third direction”)(Gawase fig 17, 19); a second conductor (Gawase 24, ¶0131) provided above the first conductor and extending in the first direction (Gawase fig 17, 19); an oxide semiconductor layer (Gawase 10, ¶0035) provided between the first conductor and the second conductor and extending in the first direction (Gawase fig 17, 19); a conductive oxide layer (Gawase 18a, ¶0076) between the second conductor and the oxide semiconductor layer (Gawase fig 17); a first conductive layer (Gawase 18b, ¶0079, 0081) between the conductive oxide layer and the second conductor (Gawase fig 17); and a first insulating layer (Gawase 20, ¶0085) in contact with the conductive oxide layer (Gawase fig 17), wherein a portion of the conductive oxide layer is between and aligned with the first insulating layer and the oxide semiconductor layer in the first direction (Gawase fig 17). Regarding claim 2, Gawase discloses: The semiconductor device according to claim 1, further comprising: a second conductive layer (Gawase 12, ¶0042) extending in a second direction (Gawase “first direction”) intersecting the first direction (Gawase “third direction”) and surrounding the oxide semiconductor layer (Gawase 10)(Gawase fig 17, 19, ¶0042); and an insulating film (Gawase 14, ¶0044) provided between the oxide semiconductor layer and the second conductive layer and in contact with the oxide semiconductor layer and the second conductive layer (Gawase fig 17, 19, ¶0044). Regarding claim 3, Gawase discloses: The semiconductor device according to claim 2, wherein the insulating film (Gawase 14) contains at least one element selected from the group consisting of silicon (Si), aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), tantalum (Ta), vanadium (V), and magnesium (Mg), and oxygen (Gawase ¶0045, “silicon oxide or aluminum oxide ”). Regarding claim 4, Gawase discloses: The semiconductor device according to claim 1, wherein the semiconductor substrate (Gawase 250) includes a circuit having a complementary field effect transistor (Gawase ¶0142). Regarding claim 5, Gawase discloses: The semiconductor device according to claim 1, wherein the conductive oxide layer (Gawase 18a) contains a metal oxide of indium-tin-oxide (ITO)(Gawase ¶0076-0077). Regarding claim 9, Gawase discloses: The semiconductor device according to claim 1, wherein the oxide semiconductor layer (Gawase 10) contains indium oxide and gallium oxide, indium oxide and zinc oxide, or indium oxide and tin oxide (Gawase ¶0038). Regarding claim 10, Gawase discloses: The semiconductor device according to claim 1, wherein the first conductive layer (Gawase 18b) contains at least one material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), and ruthenium (Ru)(Gawase ¶0079-0080). Regarding claim 11, Gawase discloses: The semiconductor device according to claim 1, wherein the first insulating layer (Gawase 20) contains at least one material selected from the group consisting of aluminum oxide (AlOx), zirconium oxide (ZrOx), silicon nitride (SiNx), and silicon oxide (SiOx)(Gawase ¶0085) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gawase et al (US 20220302320 A1, foreign priority to JP 2021044169 A, published 17 Mar 2021, hereafter Gawase) , as applied to claim 1 above, and further in view of Ramaswamy et al (US 20200111800 A1, hereafter Ramaswamy) . Regarding claim 6, Gawase teaches: The semiconductor device according to claim 1. Gawase does not teach: a second insulating layer in contact with a first side wall of the first conductive layer, and separating the first conductive layer from the first insulating layer. Ramaswamy, in the same field of endeavor of semiconductor device manufacturing, teaches: a second insulating layer (Ramaswamy 126, ¶0045) in contact with a first side wall of a first conductive layer (Ramaswamy 120, ¶0038), and separating the first conductive layer from a first insulating layer (Ramaswamy 122, ¶0041)(Ramaswamy fig 7, 13, ¶0066). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gawase to include a second insulating layer “in contact with a first side wall of the first conductive layer, and separating the first conductive layer from the first insulating layer”, as taught by Ramaswamy, in order to provide lateral dimensional control of a dielectric along a sidewall (Ramaswamy ¶0047) . 07-22-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Gawase et al (US 20220302320 A1, foreign priority to JP 2021044169 A, published 17 Mar 2021, hereafter Gawase) , as applied to claim 1 above, and further in view of Sawabe et al (US 20200303554 A1, hereafter Sawabe) . Regarding claim 8, Gawase teaches: The semiconductor device according to claim 1. Gawase does not teach: a second conductive layer between the conductive oxide layer and the second conductor. Sawabe, in the same field of endeavor of semiconductor device manufacturing, teaches: a second conductive layer (Sawabe 12, ¶0028, W portion of 12 ) between a conductive oxide layer (Sawabe 12, ¶0028, ITO portion of 12 ) and a second conductor (Sawabe 22)(Sawabe fig 1, 2, ¶0028). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Gawase to include a second conductive layer “between the conductive oxide layer and the second conductor”, as taught by Sawabe, in order to provide a composite electrode (Sawabe ¶0028), thereby reducing contact resistance . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 12-17, 19, and 20 are allowed. 07-43-02 AIA Claim s 7 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7 , it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations: wherein the second insulating layer is not in contact with a second side wall of the first conductive layer that is on an opposite side of the first conductive layer from the first side wall in the second direction. (Applicant fig 5A, ¶0084). Gawase in view of Ramaswamy, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Gawase, Ramaswamy, Sawabe, Kawai, or any other prior arts of record so that all of limitations of claim 7 as a whole can be met. Regarding claim 12 , it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations: a second conductive layer disposed on the first conductive layer, and having an inverted trapezoidal shape when viewed in the first direction; a first insulating layer in contact with the conductive oxide layer and having a portion that is between the conductive oxide layer and the first and second conductive layers in a second direction intersecting the first direction . (Applicant fig 7, 9F, ¶0096, 0111). Gawase et al (US 20220302320 A1, hereafter Gawase) teaches: A semiconductor device (Gawase MC 1, 210, fig 17, 19, 21) comprising: a semiconductor substrate (Gawase 250, ¶0145); a memory capacitor (Gawase 201, ¶0167) provided on the semiconductor substrate (Gawase fig 19); a first conductor (Gawase 22, ¶0133) provided above the memory capacitor and extending in a first direction (Gawase “third direction”)(Gawase fig 17, 19); a second conductor (Gawase 18, 24, ¶0131) provided above the first conductor and extending in the first direction (Gawase fig 17, 19); the second conductor including a conductive oxide layer (Gawase 18a, ¶0076), a first conductive layer (Gawase 18b, ¶0079, 0081) disposed on the conductive oxide layer (Gawase fig 17); an oxide semiconductor layer (Gawase 10, ¶0035) provided between the first conductor and the conductive oxide layer of the second conductor and extending in the first direction (Gawase fig 17, 19); and a first insulating layer (Gawase 20, ¶0085) in contact with the conductive oxide layer (Gawase fig 17). Sawabe et al (US 20200303554 A1, hereafter Sawabe) teaches: a second conductive layer disposed on the first conductive layer. Therefore, Gawase in view of Sawabe, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Gawase, Ramaswamy, Sawabe, Kawai, or any other prior arts of record so that all of limitations of claim 12 as a whole can be met. Regarding claims 13-16 , the dependent claims are allowed for their dependency to claim 12. Regarding claim 17 , it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations: the second conductor including a conductive oxide layer and having an inverted trapezoidal shape when viewed in the first direction. (Applicant fig 7, 9F, ¶0096, 0111). Gawase et al (US 20220302320 A1, hereafter Gawase) teaches: A semiconductor device (Gawase MC 1, 210, fig 17, 19, 21) comprising: a semiconductor substrate (Gawase 250, ¶0145); a memory capacitor (Gawase 201, ¶0167) provided on the semiconductor substrate (Gawase fig 19); a first conductor (Gawase 22, ¶0133) provided above the memory capacitor and extending in a first direction (Gawase “third direction”)(Gawase fig 17, 19); a second conductor (Gawase 18, 24, ¶0131) provided above the first conductor and extending in the first direction (Gawase fig 17, 19); the second conductor including a conductive oxide layer (Gawase 18a, ¶0076), a first conductive layer (Gawase 18b, ¶0079, 0081) disposed on the conductive oxide layer (Gawase fig 17); an oxide semiconductor layer (Gawase 10, ¶0035) provided between the first conductor and the conductive oxide layer of the second conductor and extending in the first direction (Gawase fig 17, 19); and a first insulating layer (Gawase 20, ¶0085) in contact with the second conductor and having a portion that extends into the second conductor so that a bottom surface of the first insulating layer is below an upper surface of the second conductor (Gawase fig 17, a portion of 20 below 18 ). Sawabe et al (US 20200303554 A1, hereafter Sawabe) teaches: a second conductive layer disposed on the first conductive layer. Therefore, Gawase in view of Sawabe, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Gawase, Ramaswamy, Sawabe, Kawai, or any other prior arts of record so that all of limitations of claim 17 as a whole can be met. Regarding claims 19 and 20 , the dependent claims are allowed for their dependency to claim 17 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS B. MICHAUD/ EXAMINER Art Unit 2818 /Mounir S Amer/Primary Examiner, Art Unit 2818 Application/Control Number: 18/593,988 Page 2 Art Unit: 2818 Application/Control Number: 18/593,988 Page 3 Art Unit: 2818 Application/Control Number: 18/593,988 Page 4 Art Unit: 2818 Application/Control Number: 18/593,988 Page 5 Art Unit: 2818 Application/Control Number: 18/593,988 Page 6 Art Unit: 2818 Application/Control Number: 18/593,988 Page 7 Art Unit: 2818 Application/Control Number: 18/593,988 Page 8 Art Unit: 2818 Application/Control Number: 18/593,988 Page 9 Art Unit: 2818 Application/Control Number: 18/593,988 Page 10 Art Unit: 2818
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