DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17, in the reply filed on 06/08/2026 is acknowledged. Claims 18-20 are therefore withdrawn.
Status of the Application
Claims 1-20 remain pending in this application. Claims 18-20 are withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 3, 6, and 7 are objected to because of the following informalities:
Regarding claims 3, it recites “an insulating film”, it should read “asecond insulating film”, “the
Regarding claims 6, it recites “an insulating film”, it should read “asecond insulating film”, “the
Regarding claim 7, it recites “the base cylindrical portion”, it should read “the base portion”, or another appropriate correction.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, it recites the limitation "the first direction" in line 4. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a first direction”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Regarding claim 15, it recites the limitation "the first semiconductor" in line 13. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the first semiconductor layer”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Regarding claims 16 and 17, the claims depend from rejected claim 15, includes all limitations of the claim and therefore are rejected for the same reason. The claims will be examined on the basis of interpretation of the rejected claim hereafter.
Allowable Subject Matter
Claims 1-14 are allowed.
Claim 15-17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
the cylindrical base portion extending further in a radial direction than the upper surface of the first conductive layer such that a diameter R2 thereof is greater than the diameter R1. (Applicant fig 2A, ¶0036, 0048).
Lee et al (US 20230011675 A1, hereafter Lee) teaches: A semiconductor memory device (Lee figs 1-3, ¶0003, 0004) comprising:
a ferroelectric memory (Lee SS, ¶0026, 0050, 0241, figs 1-3) that includes a first conductive layer (Lee GE, ¶0029, 0031) extending in a first direction (Lee D1)(Lee figs 1, 3, ¶0029) and having a cylindrical shape (Lee figs 1, 2) and an upper surface that has a diameter R1 (Lee fig 2),
a first semiconductor layer (Lee CH, OP1, ¶0033, 0035, 0044) extending in the first direction (Lee figs 1, 3),
a ferroelectric layer (Lee FP, ¶0036) extending in the first direction (Lee figs 1, 3) and surrounded by the first semiconductor layer (Lee figs 1, 3),
a second conductive layer (Lee MP, ¶0038) extending in the first direction (Lee figs 1, 3) in contact with the ferroelectric layer (Lee figs 1, 3, ¶0038), and
a third conductive layer (Lee CL1, ¶0027) in contact with an outer periphery of the first semiconductor layer (Lee figs 1, 3, ¶0046).
Chang et al (US 20230209836 A1, hereafter Chang) teaches: A semiconductor memory device (Chang 1, ¶0002, 0032, 0036) comprising:
a ferroelectric memory (Lee 94, 200, ¶0037, 0083, figs 1, 2) that includes a first conductive layer (Chang 39, ¶0049, 0058, at least capable thereof) having a cylindrical shape (Chang fig 1) and an upper surface that has a diameter R1 (Chang fig 1),
a first semiconductor layer (Chang 71, ¶0037) extending in a first direction (Chang figs 1, 2, vertically), and having a cylindrical base portion in contact with the upper surface of the first conductive layer (Chang fig 1, ¶0049),
a ferroelectric layer (Chang 83, ¶0040, 0083) extending in the first direction (Chang fig 1),
a second conductive layer (Chang 81, ¶0033, 0040, 0071) surrounded by and in contact with the ferroelectric layer (Chang figs 1, 2), and
a third conductive layer (Chang 75, ¶0044) in contact with the first semiconductor layer (Chang fig 1, ¶0044).
Jing et al (US 20240172450 A1, hereafter Jing) teaches: A semiconductor memory device (Jing 300, 310, ¶105-0106, 0137, figs 4, 9a, 9b) comprising:
a ferroelectric memory (Jing 400, ¶0106, 0137, fig 4, 9b) that includes a first conductive layer (Jing 52, ¶0126, 0132) extending in a first direction (Jing Z, ¶0115)(Jing fig 9b, at least having a vertical extent) and having a cylindrical shape (Jing 9a) and an upper surface that has a diameter R1 (Jing figs 9a, 9b),
a first semiconductor layer (Jing 53) extending in the first direction (Jing fig 9b), and having a cylindrical base portion in contact with the upper surface of the first conductive layer (Jing fig 9b, top of 53 in contact with 52),
a ferroelectric layer (Jing 63, ¶0122, 0131) extending in the first direction (Jing fig 9b),
a second conductive layer (Jing 61, ¶0126, 0132) extending in the first direction (Jing fig 9b) and surrounded by and in contact with the ferroelectric layer (Jing fig 9b), and
a third conductive layer (Jing 51, ¶0126, 0132) in contact with an outer periphery of the first semiconductor layer (Jing fig 9b).
Neither Lee, Chang, nor Jing, either alone or in combination, teaches: the cylindrical base portion extending further in a radial direction than the upper surface of the first conductive layer such that a diameter R2 thereof is greater than the diameter R1, as required by claim 1.
Therefore, Lee in view of Chang and Jing in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Lee, Chang, Jing, or any other prior arts of record so that all of limitations of claim 1 as a whole can be met.
Regarding claims 2-14, the dependent claims are allowed for their dependency to claim 1.
Regarding claim 15, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the first conductive layer has a cylindrical base portion that has a larger diameter than and is in contact with the cylindrical base portion of the first semiconductor (as best understood to mean “the first semiconductor layer”). (Applicant fig 2A, ¶0036, 0048).
Lee et al (US 20230011675 A1, hereafter Lee) teaches: A semiconductor memory device (Lee figs 1-3, ¶0003, 0004) comprising:
a ferroelectric memory (Lee SS, ¶0026, 0050, 0241, figs 1-3) that includes
a first conductive layer (Lee GE, ¶0029, 0031),
a first semiconductor layer (Lee CH, OP1, ¶0033, 0035, 0044) extending in the first direction (as best understood to mean “a first direction”)(Lee D1)(Lee figs 1, 3),
a ferroelectric layer (Lee FP, ¶0036) extending in the first direction (Lee figs 1, 3) and surrounded by the first semiconductor layer (Lee figs 1, 3),
a second conductive layer (Lee MP, ¶0038) extending in the first direction (Lee figs 1, 3) in contact with the ferroelectric layer (Lee figs 1, 3, ¶0038), and
a third conductive layer (Lee CL1, ¶0027) in contact with an outer periphery of the first semiconductor layer (Lee figs 1, 3, ¶0046).
Chang et al (US 20230209836 A1, hereafter Chang) teaches: A semiconductor memory device (Chang 1, ¶0002, 0032, 0036) comprising:
a ferroelectric memory (Lee 94, 200, ¶0037, 0083, figs 1, 2) that includes
a first conductive layer (Chang 39, ¶0049, 0058, at least capable thereof),
a first semiconductor layer (Chang 71, ¶0037) extending in the first direction (as best understood to mean “a first direction”)(Chang figs 1, 2, vertically) and having a cylindrical base portion in contact with the first conductive layer (Chang fig 1, ¶0049),
a ferroelectric layer (Chang 83, ¶0040, 0083) extending in the first direction (Chang fig 1),
a second conductive layer (Chang 81, ¶0033, 0040, 0071) surrounded by and in contact with the ferroelectric layer (Chang figs 1, 2), and
a third conductive layer (Chang 75, ¶0044) in contact with an inner periphery of the first semiconductor layer (Chang fig 1, ¶0044),
wherein the first conductive layer has a cylindrical base portion that has a larger diameter than and is in contact with the cylindrical base portion of the first semiconductor (as best understood to mean “the first semiconductor layer”)(Chang fig 1, 69 having a horizontal portion 30 in the diameter direction of 71 and 39, therefore a top surface of 39 having a cylindrical shape has a larger diameter than a diameter of a bottom surface of 71 having a cylindrical shape in contact 39).
Jing et al (US 20240172450 A1, hereafter Jing) teaches: A semiconductor memory device (Jing 300, 310, ¶105-0106, 0137, figs 4, 9a, 9b) comprising:
a ferroelectric memory (Jing 400, ¶0106, 0137, fig 4, 9b) that includes
a first conductive layer (Jing 52, ¶0126, 0132),
a first semiconductor layer (Jing 53) extending in the first direction (as best understood to mean “a first direction”)(Jing fig 9b) and having a cylindrical base portion in contact with the first conductive layer (Jing fig 9b, top of 53 in contact with 52),
a ferroelectric layer (Jing 63, ¶0122, 0131) extending in the first direction (Jing fig 9b), and
a second conductive layer (Jing 61, ¶0126, 0132) extending in the first direction (Jing fig 9b) and surrounded by and in contact with the ferroelectric layer (Jing fig 9b), and
a third conductive layer (Jing 51, ¶0126, 0132) in contact with an outer periphery of the first semiconductor layer (Jing fig 9b).
Neither Lee, Chang, nor Jing, either alone or in combination, teaches: the cylindrical base portion extending further in a radial direction than the upper surface of the first conductive layer such that a diameter R2 thereof is greater than the diameter R1, as required by claim 15.
Therefore, Lee in view of Chang and Jing in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Lee, Chang, Jing, or any other prior arts of record so that all of limitations of claim 15 as a whole can be met.
Regarding claims 16 and 17, the dependent claims are allowable for their dependency to claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Moon et al (US 20230267995 A1) is cited as an example of an analogous device further showing a conical semiconductor channel with tapered radii surrounded by a ferroelectric layer and conductor.
Sato (US 20200227439 A1) is cited as an example of an analogous 3D ferroelectric memory device with a source electrode directly contacting and surrounding an annular source region of a vertical channel.
Makala et al (US 20210358952 A1) is cited as an example of an analogous 3D ferroelectric memory device with MFMIS-type stack.
Rabkin et al (US 20220310656 A1) is cited as an example of an analogous device with a vertical channel employing a ferroelectric semiconductor.
Arai et al (US 20200135242 A1) is cited as an example of an analogous vertical memory pillar with direct conductor to semiconductor contact.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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