Prosecution Insights
Last updated: July 17, 2026
Application No. 18/594,103

LIGHT DETECTING DEVICE AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Mar 04, 2024
Priority
Mar 31, 2021 — JP 2021-062418 +2 more
Examiner
NARAGHI, ALI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
672 granted / 778 resolved
+18.4% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
28 currently pending
Career history
810
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
87.1%
+47.1% vs TC avg
§102
4.9%
-35.1% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 778 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4,7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki (WO 2018139279, wherein it’s American version is US Pub No. 20210134863). With respect to claim 1, Suzuki discloses a first pixel (upper left pixel, Fig.6a) provided on a semiconductor substrate (where 12 is formed); and an isolation region (51,51a) that isolates the first pixel from an adjacent pixel (other pixels,Fig.6a), wherein the first pixel is surrounded by first to fourth portions of the isolation region in plan view (the four sides of 51), the isolation region includes a fifth portion (51a top) and a sixth portion (51a bottom) provided between the first portion and the third portion in the plan view (Fig.6a), a contact region is provided between the fifth portion and the sixth portion in the plan view (FD and TG), and the fifth portion is in contact with the first portion (Fig.6a), and the sixth portion is in contact with the third portion (Fig.6a). With respect to claim 2, Suzuki discloses wherein an angle formed by the first portion and the fifth portion is perpendicular (Fig.6a). With respect to claim 3, Suzuki discloses wherein the first portion and the third portion face each other (Fig.6a). With respect to claim 4, Suzuki discloses wherein the fifth portion, the contact region, and the sixth portion are arranged in this order along a first direction in the plan view (in the y direction). With respect to claim 7, Suzuki discloses wherein the trench penetrates the semiconductor substrate (Fig.6b). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5-6,8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (WO 2018139279, wherein it’s American version is US Pub No. 20210134863), in view of Koyama et al (US Pub No. 20200075660). . With respect to claim 5, Suzuki does not explicitly disclose, wherein the first pixel includes a first transistor and a second transistor provided on both sides of the sixth portion, and a first contact, a gate electrode, and a second contact of the first transistor are arranged in this order along the first direction. On the other hand, Koyama discloses wherein the first pixel (upper left portion, Fig.5A, Fig.5B) includes a first transistor (3 to the left of 10 for the upper left pixel,Fig.5A) and a second transistor (3 to the right of 10 for the upper left pixel,Fig.5A) provided on both sides of the sixth portion (which would around 10 in 5A-B), and a first contact, a gate electrode (the gate for the left transistor), and a second contact of the first transistor (source or drain for left transistor) are arranged in this order along the first direction (the y direction). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Suzuki according to the teachings of the Koyama such that transistors are formed left and the right of the 5th portion, in order to reset the pixel and process the light captured by the pixel. With respect to claim 6, Koyama discloses wherein a third contact (for the source or drain contact of the right transistor), a gate electrode (the gate for the right transistor), and a fourth contact (for the source or drain of the right transistor) of the second transistor are arranged in this order along the first direction (in the y direction). With respect to claim 8, Suzuki does not explicitly disclose wherein the contact region is provided at a center of the first pixel. On the other hand, Koyama discloses wherein the contact region (the well connected to 10 Fig.5B) is provided at a center of the first pixel (Fig.5A-B). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Suzuki according to the teachings of the Koyama such that the contact region is provided at a center of the pixel, in order to increase the size of the pixel, thereby increasing the amount of light signal collected by the pixel, and cutting the cost. With respect to claim 9, the arts cited above do not explicitly disclose wherein the contact region is a p-type impurity region. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that that the contact region is a p-type well in order to prevent the electrons from the neighboring regions penetrate other parts thereby reducing cross talk, and improving the pixel performance. With respect to claim 10, Koyama discloses wherein the contact region is provided on the semiconductor substrate (404, Fig.5B). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALI NARAGHI/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 04, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.4%)
2y 6m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 778 resolved cases by this examiner. Grant probability derived from career allowance rate.

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