CTNF 18/594,167 CTNF 99791 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. General Remarks 07-06 AIA 15-10-15 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection. 3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. 4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Drawings 06-22 AIA 5. The drawings are objected to because coordinate axes indicating directions for Figures 1A/1B, 2A/2B, 3A/3B and 5A/5B are missing . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA 6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: “Well Tap Cells with Integrated Protection Diodes” Appropriate correction is required . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA 8. Claim s 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu, Chia-Lin et al. (Pub No. US 20240371854 A1) (hereinafter, Hsu) . Hsu, Fig 1A: (Pertaining to claims 1-20) Illustrates a cross-sectional view of the integrated circuit device PNG media_image1.png 412 706 media_image1.png Greyscale Re Claim 1, Hsu teaches a semiconductor structure comprising: at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]); and at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]; Note: Figs 3A/3B are comprise protection devices/diodes 300A/300B per ¶[0066])), wherein the at least one bias structure is connected to the at least one protection diode through at least one contact line (Coupled through contact line (not labelled) to P-well PW1, connecting to source/drains; Fig 1A; ¶[0034]). (See Figs 3A/3B below) Hsu, Figs 3A/3B: (Pertaining to claims 1-20) cross-sectional views of protection devices (diodes) in accordance with embodiments. PNG media_image2.png 378 553 media_image2.png Greyscale Note: Protection devices 300A/300B may correspond to PID protection devices of circuits 171-174 of Figure 1A above Re Claim 2, Hsu teaches the semiconductor structure of claim 1, wherein the at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) is formed in a first portion (P-well; PW1; Fig 1A; ¶[0034]) of a substrate (Substrate; 110; Fig 1A; ¶[0015]) having a first doping type (P-type; ¶[0015]), and the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]) is formed in a second portion (N-Well; NW; Fig 3A; ¶[0069]) of the substrate having a second doping type (N-type; ¶[0071]) opposite the first doping type. Re Claim 3, Hsu teaches the semiconductor structure of claim 2, wherein the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]) has the first doping type (P-type; i.e. P-type Diode 300A; Fig 3A; ¶[0066]). Re Claim 4, Hsu teaches the semiconductor structure of claim 2, wherein the first doping type (P-type; i.e. P-type Diode 300A; Fig 3A; ¶[0066]) is p-type and the at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) is connected to a source voltage (VSS) (VSS, i.e. source/drain 124 is connected to body contact 125 which connects to source voltage VSS; Fig 1A; ¶[0021]). Re Claim 5, Hsu teaches the semiconductor structure of claim 4, wherein the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]) comprises a p-type diffusion region (P-type source/drains; 133/134; Fig 1A; ¶[0022]) formed in an n-well (N-well; NW1; Fig 1A; ¶[0022]). Re Claim 6, Hsu teaches the semiconductor structure of claim 2, wherein the first doping type (First doping type of at least one bias structure, i.e. source/drains 123/124, as applied to claim 2, may be N-type; Fig 1A; ¶[0022]) is n-type and the at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) is connected to a power voltage (VDD) (Power supply voltage (VDD); ¶[0022]). Re Claim 7, Hsu teaches the semiconductor structure of claim 6, wherein the second doping type (Second doping type of the protection diode may be P-type, i.e. P-type diode 300A; Fig 3A; ¶[0066]) is p-type and the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]) comprises an n-type diffusion region (N-doped region; 316; Fig 3A; ¶[0070]) formed in the second portion (N-Well; NW; Fig 3A; ¶[0069]) of the substrate (Substrate; 310; Fig 3A; ¶[0067]) having the second doping type (Per ¶[0072] the substrate 310 is a p-type substrate). Re Claim 8, Hsu teaches the semiconductor structure of claim 2 further comprising: at least one other bias structure (P-doped and n-doped regions; 315/316 325/326; Figs 3A/3B; ¶[0067]) formed in the second portion (N-Well; NW; Fig 3A; ¶[0069]) of the substrate (Substrate; 310; Fig 3A; ¶[0067]); and at least one other protection diode (Diode; 329; Fig 3B; ¶[0074]) formed in the first portion (P-well; PW; Fig 3B; ¶[0074]) of the substrate, wherein the at least one other bias structure is connected to the at least one other protection diode through at least one other contact line (Conductive structure; 317; Fig 3A; ¶[0070]). Re Claim 9, Hsu teaches the semiconductor structure of claim 1, wherein: The at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) and the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]; Note: Figs 3A/3B are comprise protection devices/diodes 300A/300B per ¶[0066])) are elements of a well tap cell (Fig 1A may be considered a well tap cell, i.e. body contacts are known as well taps per ¶[0021] and VSS connects to p-well to VSS and n-well to VDD; ¶¶[0022-0023]); and the semiconductor structure further comprises a filler cell (Cell (not labelled) comprising PID protection circuit 179 which may replace PID protection circuits 171-174 comprising protection diodes; Fig 1B; ¶¶[0051-0052]) comprising at least one other protection diode (PID protection circuit; 179; Fig 1B; ¶¶[0051-0052]). Re Claim 10, Hsu teaches a semiconductor structure comprising: at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) comprising a first diffusion region (Body contact; 125; Fig 1A; ¶[0021]) having a designated doping type (P-doped; ¶[0021]); and at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]; Note: Figs 3A/3B are comprise protection devices/diodes 300A/300B per ¶[0066])) comprising a second diffusion region (P-doped region; 315; Fig 3A; ¶[0067]) having the designated doping type, wherein the at least one bias structure is connected to the at least one protection diode through at least one contact line (Coupled through contact line (not labelled) to P-well PW1, connecting to source/drains; Fig 1A; ¶[0034]). Re Claim 11, Hsu teaches the semiconductor structure of claim 10, wherein the first diffusion region (Body contact; 125; Fig 1A; ¶[0021]) is formed in a portion (P-well; PW1; Fig 1A; ¶[0017]) of a substrate (Substrate; 110; Fig 1A; ¶[0015]) having a same doing type (P-type; ¶[0017]) as the designated doping type. Re Claim 12, Hsu teaches the semiconductor structure of claim 10, wherein the second diffusion region (P-doped region; 315; Fig 3A; ¶[0067]) is formed in a portion (N-well; NW; Fig 3A; ¶[0068]) of a substrate (Substrate; 310; Fig 3A; ¶[0067]) having a different doping type (Designated doping type is p-type, whereas n-well is n-doped; ¶[0068]) from the designated doping type. Re Claim 13, Hsu teaches the semiconductor structure of claim 10, wherein the designated doping type (P-doped; ¶[0021]) is p-type and the at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) is connected to a source voltage (VSS) (VSS, i.e. source/drain 124 is connected to body contact 125 which connects to source voltage VSS; Fig 1A; ¶[0021]). Re Claim 14, Hsu teaches the semiconductor structure of claim 10, wherein the designated doping type (First doping type of at least one bias structure, i.e. source/drains 123/124, may be N-type; Fig 1A; ¶[0022]) is n-type and the at least one bias structure (Source/drains & body contacts; 123/124 133/134 143/144 153/154 & 125/135/145/155; Fig 1A; ¶[0020]) is connected to a power voltage (VDD) (Power supply voltage (VDD); ¶[0022]). Re Claim 15, Hsu teaches the semiconductor structure of claim 10, wherein the at least one protection diode (PID protection devices/diodes; 175/176 319/329 300A/300B; Figs 1A/3A/3B; ¶[0034]; Note: Figs 3A/3B are comprise protection devices/diodes 300A/300B per ¶[0066])) is a plasma charge protection diode (Plasma induced gate oxide damage (PID) diode is intended to prevent breakdown of underlying gate dielectric and damage to the corresponding transistor from plasma operations leaving charges accumulating in conductive regions, i.e. a plasma charge protection diode; ¶[0012]). Re Claim 16, Hsu teaches a cell comprising: a substrate (Substrate; 110; Fig 1A; ¶[0015]) comprising a p-type portion (P-substrate/P-well; 110/PW; Fig 1A) and an n-type portion (Deep n-wells/N-well; DNW-A/DNW-B/NW1; Fig 1A; ¶[0016]), wherein the n-type portion comprises an n-well (N-wells; ¶[0016]); a p-type bias structure (Body contact; 125; Fig 1A; ¶[0021]) comprising a first p-type diffusion region (Body contact; 125; Fig 1A; ¶[0021]) formed in the p-type portion (P-well; PW1; Fig 1A; ¶[0021]); a p-type protection diode (PID protection devices; 300A; Fig 3A; ¶[0034]) comprising a second p-type diffusion region (P-doped region; 315; Fig 3A; ¶[0067]) formed in the n-well (N-well; 311; Fig 3A; ¶[0067]); an n-type bias structure (Body contact; 135/155; Fig 1A; ¶[0022]) comprising a first n-type diffusion region (Body contact; 135; Fig 1A; ¶[0022]) formed in the n-well; an n-type protection diode (PID protection devices; 300B; Fig 3B; ¶[0034]) comprising a second n-type diffusion region (N-doped region; 325; Fig 3B; ¶[0072]) formed in the p-type portion; wherein the p-type bias structure is connected to the p-type protection diode through a first contact line (Contact line (not labelled); Note: Body contact 125 connects through contact line to PID device 171 which may also be represented per ¶[0066] as PID device 300A; Figs 1A/3A; ¶[0034]); and wherein the n-type bias structure is connected to the n-type protection diode through a second contact line (Contact line (not labelled); Note: Body contact 155 connects through contact line to PID device 172 which may also be represented per ¶[0071] as PID device 300B; Figs 1A/3B; ¶[0034]). Re Claim 17, Hsu teaches the cell of claim 16, wherein the p-type bias structure (Body contact; 125; Fig 1A; ¶[0021]) is connected to a source voltage (VSS) (Per ¶[0021] in some embodiments, the body contact 125 is configured as a common electrical connection from the P-well PW1 to both the PID protection circuit 171 and VSS). Re Claim 18, Hsu teaches the cell of claim 16, wherein the n-type bias structure (Body contact; 135/155; Fig 1A; ¶[0022]) is connected to a power voltage (VDD) (Per ¶[0022] In some embodiments, the body contact 135 is configured as a common electrical connection from the N-well NW1 to both a PID protection circuit and VDD). Re Claim 19, Hsu teaches the cell of claim 16, wherein the p-type protection diode (PID protection devices; 300A; Fig 3A; ¶[0034]) and the n-type protection diode (PID protection devices; 300B; Fig 3B; ¶[0034]) are reverse bias diodes (PID protection devices 300A/300B may comprise of reverse diodes 175/176/177/178; Figs 1A/3A/3B; ¶[0034,0038]). Re Claim 20, Hsu teaches the cell of claim 16, wherein the p-type protection diode (PID protection devices; 300A; Fig 3A; ¶[0034]) and the n-type protection diode (PID protection devices; 300B; Fig 3B; ¶[0034]) are plasma charge protection diodes (Plasma induced gate oxide damage (PID) diode is intended to prevent breakdown of underlying gate dielectric and damage to the corresponding transistor from plasma operations leaving charges accumulating in conductive regions, i.e. a plasma charge protection diode; ¶[0012]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. [1] Salcedo; Javier Alejandro et al. (Pub No. US 20140167105 A1) teaches a protection device includes silicon-controlled rectifiers (SCR) and diodes for providing protection between a signal node and a power high supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. [2] Lin; Ming-Te et al. (Pub No. US 20250031458 A1) discloses a semiconductor structure comprising of well-regions with diffusion regions located in well regions, surrounding gate and gate dielectric layers. The semiconductor device is primarily designed to prevent plasma induced damage (PID). Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.E.D./ Examiner Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 18/594,167 Page 2 Art Unit: 2817 Application/Control Number: 18/594,167 Page 3 Art Unit: 2817 Application/Control Number: 18/594,167 Page 4 Art Unit: 2817 Application/Control Number: 18/594,167 Page 5 Art Unit: 2817 Application/Control Number: 18/594,167 Page 6 Art Unit: 2817 Application/Control Number: 18/594,167 Page 7 Art Unit: 2817 Application/Control Number: 18/594,167 Page 8 Art Unit: 2817 Application/Control Number: 18/594,167 Page 9 Art Unit: 2817 Application/Control Number: 18/594,167 Page 10 Art Unit: 2817 Application/Control Number: 18/594,167 Page 11 Art Unit: 2817 Application/Control Number: 18/594,167 Page 12 Art Unit: 2817 Application/Control Number: 18/594,167 Page 13 Art Unit: 2817
