CTNF 18/594,210 CTNF 99642 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 15-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Per MPEP 2173.05 II. PRODUCT AND PROCESS IN THE SAME CLAIM [AltContent: rect] A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112 , second paragraph. See In re Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1318, 97 USPQ2d 1737, 1748-49 (Fed. Cir. 2011). In Katz, a claim directed to "[a] system with an interface means for providing automated voice messages…to certain of said individual callers, wherein said certain of said individual callers digitally enter data " was determined to be indefinite because the italicized claim limitation is not directed to the system, but rather to actions of the individual callers, which creates confusion as to when direct infringement occurs. Katz, 639 F.3d at 1318, 97 USPQ2d at 1749 (citing IPXL Holdings v. Amazon.com, Inc., 430 F.3d 1377, 1384, 77 USPQ2d 1140, 1145 (Fed. Cir. 2005), in which a system claim that recited "an input means" and required a user to use the input means was found to be indefinite because it was unclear "whether infringement … occurs when one creates a system that allows the user [to use the input means], or whether infringement occurs when the user actually uses the input means."); Ex parte Lyell, 17 USPQ2d 1548 (Bd. Pat. App. & Inter. 1990) (claim directed to an automatic transmission workstand and the method of using it held ambiguous and properly rejected under 35 U.S.C. 112 , second paragraph). In contrast, when a claim recites a product and additional limitations which focus on the capabilities of the system, not the specific actions or functions performed by the user, the claim may be definite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112 , second paragraph. See Mastermine Software, Inc. v. Microsoft Corp., 874 F.3d 1307, 124 USPQ2d 1618 (Fed. Cir. 2017). Claim 15 cites language of “applying a voltage” which is a process of using a product in a claim that designates a product. Thus, the language is indefinite and will be examined as best understood understanding that one could realistically apply a voltage across a resistor and get various values of voltage drops over said resistors dependent upon the voltage applied, among many other effects. Subsequently, dependent claims 16-21 further limit the indefinite independent claim, claim 15, and thus are also rejected under 35 USC 112(b). Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-4, 7-8, and 15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Yoshida (US 20100109125) . Yoshida teaches, [claim 1] An electronic device, comprising: a first diffused resistor; and a second diffused resistor (figure 2A, paragraphs 0043-0045, where element 9A, 8A, 3, 2, 4 11a and 12a comprise the first diffused resistor, and element 12b, 11b, 6, 5, 8b and 9b comprise the second diffused resistor. Note, the present disclosure does not recite the structure to be used in such a matter, but the structure is the same as the present application, and realistically could be used as two diffused resistors since they have all of the components that would make up such a structure, metal contacts, diffused region [noted as a well], and regions that surround it that are of the opposite conductivity type); wherein the first and second diffused resistors are in contact with each other to form a PN junction, wherein the PN junction is reverse-biased; (figure 2A, paragraph 0043-0045, where element 4 and element 2 are the two resistors and form a PN-junction which is reverse biased); and wherein a potential difference between the first and second resistors is constant at any point of the PN junction (figure 2A, paragraphs 0043-0045, where element 56 and element 2 which comprise, the diffused resistors would have a constant resistance between the two as they are uniformly doped and created). [claim 2] The device according to claim 1, wherein each of the first and second diffused resistors is made of a doped semiconductor material, the first and second diffused resistors being doped with opposite conductivity types (figure 2A, paragraphs 0043-0045, where element 2 is part of the first diffused resistor and is of first conductivity type, type N, and element 5 is part of the second diffused resistor and is of second conductivity type, type P). [claim 3] The device according to claim 1, wherein: the first diffused resistor comprises a first layer buried in a substrate and a first well, the first well extending from a periphery of the first layer to a first surface of the substrate, the first layer and the first well being made of a doped semiconductor material of a first conductivity type (figure 2A, paragraphs 0043-0045, where element 2 is the first layer buried in the substrate [element 1], and a first well [element 3] extends from a periphery of the diffused layer to a top portion of the substrate, where elements 2 and 3 the first layer and first well are made of the first conductivity type, type N); and the second resistor comprises a second layer resting on the first layer, the second layer being made of a doped semiconductor material of a second conductivity type opposite the first conductivity type (figure 2A, paragraphs 0043-0045, where element 5 is the second layer and rests on top of the first layer [element 2] and is of the second conductivity type, type P). [claim 4] The device according to claim 1, wherein: the second diffused resistor comprises a third doped semiconductor layer of a first conductivity type, the third doped semiconductor layer being flush with an upper surface of a substrate (figure 2A, paragraphs 0043-0045, where element 7 is the third doped layer flush with the upper surface of the substrate [element 1] and is of first conductivity type, N type); and the first resistor comprises a second layer made of a doped semiconductor material of a second conductivity type opposite the first conductivity type, the third doped semiconductor layer resting on the second layer (figure 2B, paragraphs 0043-0045, where element 5 of second conductivity type is also part of the first resistor in the Y-Y’ direction, separated from the second diffused resistor in the X-X’ plane, where element 7 [the third doped layer] sits on top of the second doped layer [element 5]). [claim 7] The device according to claim 1, wherein: the first diffused resistor comprises a semiconductor well in a substrate, the semiconductor well being doped with a doping type opposite to a doping type of the substrate (figure 2A, paragraphs 0043-0045, where element 1 is the substrate of P-type dopant, and the well in the first diffused resistor is element 2 of N-type dopant [opposite of P-type]); and the second diffused resistor comprises a third doped semiconductor layer of the doping type opposite to the doping type of the semiconductor well, the third doped semiconductor layer being flush with an upper surface of the substrate (figure 2A, paragraphs 0043-0045, where element 5 is the third layer in the second diffused resistor and is of dopant type P-type, opposite of the well [element 2] and the same as the substrate, and is also flush with an upper surface of the substrate [element 1]). [claim 8] The device according to claim 1, wherein each of the diffused resistors comprises a first end and a second end, each diffused resistor comprising (figure 2A paragraphs 0043-0045, where the first end is the left hand side and the second end is the right-hand side), at a level of the first and second ends, a semiconductor region that is more heavily doped than a rest of the diffused resistor which forms a terminal of said diffused resistor (figures 2A and 2B, where the first end in figure 2B has a more heavily doped region to form the terminal [element 4] and in figure 2A the right-hand side has a more heavily doped region to form a contact as well [element 4]). [claim 15] A device, comprising: a first region of doped semiconductor material of a first conductivity type (figure 2A, paragraphs 0043-0045, where element 2 is the first region of doped semiconductor material of first conductivity type, type N); a second region of doped semiconductor material of a second conductivity type opposite the first conductivity type (figure 2A, paragraphs 0043-0045, where element 5 is the second region of doped semiconductor material of second conductivity type, type P); a first electrical contact at a first end of the first region (figure 2 A, paragraphs 0043-0045, where element 9a is the first electrical contact at a first end of the first region); a second electrical contact at a second end of the first region (figure 2A, paragraphs 0043-0045, where element 12a is the second electrical contact at a second end of the first region [element 2]); wherein the first region forms a first diffused resistor between the first and second electrical contacts (figure 2A, paragraphs 0043-0045, where elements 9a, 3, 2, 4 11a and 12a form the first diffused resistor, though the present disclosure does not use the region as such, structurally it is the same as the present application and can in fact be used as a diffused resistor by one embodiment of the present disclosure); a third electrical contact at a first end of the second region; a fourth electrical contact at a second end of the second region (figure 2A, paragraphs 0043-0045, where element 12b and 9b are the third and fourth electrical contacts at the first and second end of the second doped region, respectively); wherein the second region forms a second diffused resistor between the third and fourth electrical contacts (figure 2A, paragraphs 0043-0045, where elements 9b, 5, 11b and 12a form the second diffused resistor, though the present disclosure does not use the region as such, structurally it is the same as the present application and can in fact be used as a diffused resistor by one embodiment of the present disclosure); wherein the first region is in contact with the second region to form a PN junction (figure 2A, paragraphs 0043-0045, where element 5 and 2 form a PN junction); wherein a first voltage difference is applied between the first and second terminals; wherein a second voltage difference is applied between the third and fourth terminals; and wherein the first and second voltage differences are configured such that the PN is reverse biased (Note: this particular limitations of a process of using and not a product, thus according to MPEP 2173.05 II – these limitations is indefinite and unclear – see 35 USC 112(b) rejection above, but it is understood that all the structure is present as described above, and thus that structure if these voltage differences were applied would be able to function in the same way) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 9-12, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20100109125) in view of Lin (US 20100123984) . Yoshida teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose [claim 9] The device according to claim 1, wherein each first and second diffused resistor comprises first and second terminals, the second terminals of the first and second diffused resistors being coupled to a same first node of application of a reference voltage. [claim 10] The device according to claim 1, further comprising a control circuit configured to supply potentials on terminals of the first and second diffused resistors. [claim 11] The device according to claim 10, wherein the control circuit comprises a first transistor series-coupled with the first diffused resistor between a second node of application of a power supply voltage and the first node and a second transistor series-coupled with the second diffused resistor between the second node and the first node, the first and second transistors being diode-mounted. [claim 12] The device according to claim 11, wherein the first transistor has a channel width-to-length ratio equal to a channel width-to-length ratio of the second transistor multiplied by a quotient of a value of a second resistance for the second diffused resistor to a value of a first resistance for the first diffused resistor. [claim 16] The device according to claim 15, further comprising a control circuit configured to supply first voltage difference between the first and second terminals and to supply the second voltage difference between the third and fourth terminals. [claim 17] The device according to claim 15, further comprising: a first transistor series-coupled with the first diffused resistor between a power supply voltage and the first terminal; and a second transistor series-coupled with the second diffused resistor the power supply node and the third terminal. [claim 18] The device according to claim 17, wherein the first and second transistors are each a diode-connected transistor. However, Lin does teach [claim 9] The device according to claim 1, wherein each first and second diffused resistor comprises first and second terminals, the second terminals of the first and second diffused resistors being coupled to a same first node of application of a reference voltage (figure 4, paragraph 0023, where elements R4 and R5 are the first and second diffused resistor and each the first and second terminals are connected to the same reference voltage [Vdd through element 441]). [claim 10] The device according to claim 1, further comprising a control circuit configured to supply potentials on terminals of the first and second diffused resistors (figure 4, paragraph 0023, where the circuit of figure 4 is a circuit that limits/controls the voltage going to the internal circuit [element 410] through the diffused resistors, where Vdd through element 441 creates the potential on both R4 [first diffused resistor] and R5 [second diffused resistor]). [claim 11] The device according to claim 10, wherein the control circuit comprises a first transistor series-coupled with the first diffused resistor between a second node of application of a power supply voltage and the first node (figure 4, paragraph 0023, where element R4 with element 441 is the first transistor series coupled with the first diffused resistor between a second node of the application power supply [Vdd] and first node of the resistor [element R4), and a second transistor series-coupled with the second diffused resistor between the second node and the first node, the first and second transistors being diode-mounted (figure 4, paragraph 0023, where the second transistor series coupled with the second diffused resistor is element R5 and 442 between the first node and second node). [claim 12] The device according to claim 11, wherein the first transistor has a channel width-to-length ratio equal to a channel width-to-length ratio of the second transistor multiplied by a quotient of a value of a second resistance for the second diffused resistor to a value of a first resistance for the first diffused resistor (figure 4, paragraph 0023, where the transistor 441 has a width-to-length ratio [intrinsic to its creation, being three dimensional in nature] which can be equal to a channel width-to-length ratio of the second transistor [element 442] since they are the same type of transistor created in a same circuit both attached to a diffused resistor with the same dimension [see figures 7 and 8 for dimensions of the resistors], such width-to-length ratio by necessity must be able to be multiplied by a quotient of a value of the second resistance for the second resistor to a value of the first resistance for the first diffused resistor as basic mathematics indicates that the two numbers are related in some way, which in the current argument is defined as the quotient value). [claim 16] The device according to claim 15, further comprising a control circuit configured to supply first voltage difference between the first and second terminals and to supply the second voltage difference between the third and fourth terminals (figure 4, paragraph 0023, where element Vdd supplies a first voltage through element 441 to the first diffused resistor [element R4] which contain the first and second contacts, and after subsequent voltage drop a second voltage is supplied to the second diffused resistor [element R5] which contain the third and fourth contacts, all controlled by the circuit of figure 4). [claim 17] The device according to claim 15, further comprising: a first transistor series-coupled with the first diffused resistor between a power supply voltage and the first terminal; (figure 4, paragraph 0023, where the first transistor series-coupled with the first diffused resistor is element 441 connected to R4 [first diffused resistor] between a power supply [Vdd] and the first terminal [of element R4]); and a second transistor series-coupled with the second diffused resistor the power supply node and the third terminal (figure 4, paragraph 0023, where element R5 and 442 is the second diffused resistor connected to the second transistor series-coupled between the power supply [element Vdd] and the third terminal [connected to the second diffused resistor]). [claim 18] The device according to claim 17, wherein the first and second transistors are each a diode-connected transistor (figure 7 and 8, figure 3 and 4, where the first and second diffused resistor [R4 and R5 in figure 3 are the same as figure 4 and thus by design are shown to incorporate a diode and thus are diode-connected transistors). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoshia to incorporate the teachings of Lin in order to optimize the circuitry surrounding the diffused resistors to utilize the resistors in a maximal capacity to allow for maximal efficiency of the circuitry by controlling the circuitry in a specific way and connecting the resistors in a specific way as well . 07-21-aia AIA Claim (s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20100109125) . Yoshida teaches all of the limitations of the parent claim, claim 1, but does not specifically state [claim 13] The device according to claim 1, wherein the device is configured so that the potential difference between the first and second resistors is zero at any point of the PN junction. However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION [AltContent: rect] A. Optimization Within Prior Art Conditions or Through Routine Experimentation Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art."). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoshida to optimize the device to have a potential difference between the resistors of the PN junction to be 0 to optimize the performance of the device by allowing no extra resistance than necessary in the device . 07-21-aia AIA Claim (s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20100109125) in view of Lin (US 20100123984) . Yoshida as modified teaches all of the limitations of the parent claim, claim 17, but does not specifically disclose [claim 19] The device according to claim 17, wherein the first transistor has a first channel width-to-length ratio and the second transistor has a second channel width-to-length ratio different from the first channel width-to-length ratio. [claim 20] The device according to claim 19, wherein a difference between the first and second channel width-to-length ratios is a function of a quotient of a resistance of the second diffused resistor to a resistance of the first diffused resistor. However, according to MPEP 2144.05 II. ROUTINE OPTIMIZATION [AltContent: rect] A. Optimization Within Prior Art Conditions or Through Routine Experimentation Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art."). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yoshida as modified to create the two transistors of Lin [elements 441 and 442] to not be identical [though they are shown to be the same type of transistor, thus it would be safe to assume they would be identical in their creation as each is attached to a diffused resistor], and thus the width-to-length ratio of the first with respect to the second could either be the same or different, of the two options routine optimization of the transistors would be obvious to have the width-to-length ratios being different than one another. Additionally, the relationship between the two devices by necessity of relation of any two numbers, are related by a multiplicative factor [could be a rational or irrational number] which in the present case corresponds to the quotient of the resistances of the two diffused resistors. Routine optimization would show that the relation of the two resistances could be tweaked to arrive at an optimal value such that the transistor width-to-length ratio is related to a quotient of the two resistances . 07-21-aia AIA Claim (s) 14 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20100109125) in view of Solomon et al (US 3836796) Yoshida teaches all of the limitations of the parent claims, claims 1 and 15, but does not specifically disclose [claims 14 and 21] A sensor, comprising: a device according to claim 15, the sensor being configured so that a measurement value of the sensor is dependent on a resistance value of one of the first and second diffused resistors. However, Solomon et al does teach, [claims 14 and 21] A sensor, comprising: a device according to claim 1, the sensor being configured so that a measurement value of the sensor is dependent on a resistance value of one of the first and second diffused resistors (col 2 lines 44-59, figure 1, where the sensor is attached to the diffused resistors [R1-R4, where R1-R2 are the first and second diffused resistors respectively] and the measurement value of the sensor is dependent upon the resistance value of the diffused resistors) It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teaching sof Yoshida with the teachings of Solomon et al to have connected the diffused resistors to a sensor measurement circuit to adequately measure, in the present case, the pressure of an area where the sensor measurement is dependent upon the resistance value of the diffused resistors so that the sensor can adequately work and measure accurately . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 20220399717), van Veldhoven et al (US 20170154949), Dirnecker et al (US 20140239449), Kodera et al (US 20130038385), Pontarollo et al (US 20100253423), and Morini (US 20080278213) . Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW JOHN ZABEL/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/594,210 Page 2 Art Unit: 2818 Application/Control Number: 18/594,210 Page 3 Art Unit: 2818 Application/Control Number: 18/594,210 Page 4 Art Unit: 2818 Application/Control Number: 18/594,210 Page 5 Art Unit: 2818 Application/Control Number: 18/594,210 Page 6 Art Unit: 2818 Application/Control Number: 18/594,210 Page 7 Art Unit: 2818 Application/Control Number: 18/594,210 Page 8 Art Unit: 2818 Application/Control Number: 18/594,210 Page 9 Art Unit: 2818 Application/Control Number: 18/594,210 Page 10 Art Unit: 2818 Application/Control Number: 18/594,210 Page 11 Art Unit: 2818 Application/Control Number: 18/594,210 Page 12 Art Unit: 2818 Application/Control Number: 18/594,210 Page 13 Art Unit: 2818 Application/Control Number: 18/594,210 Page 14 Art Unit: 2818 Application/Control Number: 18/594,210 Page 15 Art Unit: 2818 Application/Control Number: 18/594,210 Page 16 Art Unit: 2818 Application/Control Number: 18/594,210 Page 17 Art Unit: 2818 Application/Control Number: 18/594,210 Page 18 Art Unit: 2818
Prosecution Insights