Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the applicants arguments filed 07/31/2026, the amendment overcome the previous prior art rejection. However, upon further search and consideration a new rejection is formulated upon a new base reference Jeng et al (US 20140217610) below. The previous base reference, Elsherbini et al is no longer used as before but is still used as a secondary reference for claims 19 and 20 and no arguments are presented based on how it Elsherbini et al. is currently being used.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al (US 20140217610).
Jeng et al teaches
[claim 1] A semiconductor package, comprising: an interposer; a first semiconductor die below the interposer (figure 22, paragraphs 0054 and 0069, where element 1616 is an interposer, element 1312 [middle element 1312] is a first semiconductor die)
a stiffener separated from and below the interposer, and laterally separated from the first semiconductor die (figure 22, paragraphs 0069 and 0095, where element 2202 [situated between element 2106 and 1312, not on the outside as shown in the image] is the stiffener situated below the interposer [element 1616] and laterally separated from the first semiconductor die [element 1312 – where the stiffener is situated around the die]);
and a first dummy die, a second dummy die, and a second semiconductor die over the interposer, the first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer, the first semiconductor die overlap the second semiconductor die, and the second semiconductor die between the first dummy die and the second dummy die (figure 22, paragraph 0053, where the first and second semiconductor dies are elements 1202 on the left-hand side and right-hand side of the upper stack of three die [element 1202] above the interposer [element 1616], and the second semiconductor die is the middle element 1202, where the first and second semiconductor die overlap each other and the interposer element [element 1616]).
[claim 2] The semiconductor package of claim 1, wherein the first semiconductor die and the second semiconductor die are electrically connected through the interposer (figure 22, paragraph 0054, where element 1202 and 1312 [middle elements] are electrically connected through element 1616 [interposer]).
[claim 3] The semiconductor package of claim 1, further comprising a package substrate below the first semiconductor die (figure 22, paragraph 0023, where element 112 is the package substrate below the first semiconductor die middle element 1312]).
[claim 4] The semiconductor package of claim 3, wherein the stiffener surrounds at least a portion of the first semiconductor die (figure 22, paragraph 0095, where element 2202 is the stiffener that surrounds element 1312 [note element 2202 under element 1616 between element 2106 and 1312 is the stiffener element 2202, not the outside element 2202]).
[claim 8] The semiconductor package of claim 7, wherein the width of the interposer is greater than a width of the first semiconductor die (figure 22, paragraphs 0054 and 0069, where element 1616 [interposer] has a width greater than the first semiconductor die [middle element 1312]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610).
Jeng et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 7] The semiconductor package of claim 1, wherein a width of the interposer is greater than a sum of a width of the second semiconductor die, a width of the first dummy die, and a width of the second dummy die.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified Jeng et al to extend the length of the interposer beyond the length of first and second dummy die and second semiconductor die in order to compensate for any extra length of the semiconductor die below the interposer and allow for extra structural stability and more electrical connections for the die.
Regarding claim 10,
Jeng et al teaches
[claim 10] A semiconductor package, comprising: an interposer; a first semiconductor die below the interposer (figure 22, paragraphs 0054 and 0069, where element 1616 is an interposer, element 1312 [middle element 1312] is a first semiconductor die);
a stiffener separated from and below the interposer, and laterally separated from the first semiconductor die (figure 22, paragraphs 0069 and 0095, where element 2202 [situated between element 2106 and 1312, not on the outside as shown in the image] is the stiffener situated below the interposer [element 1616] and laterally separated from the first semiconductor die [element 1312 – where the stiffener is situated around the die]),
and a first dummy die, a second dummy die, and a second semiconductor die over the interposer, the second semiconductor die between the first dummy die and the second dummy die (figure 22, paragraph 0053, where the first and second semiconductor dies are elements 1202 on the left-hand side and right-hand side of the upper stack of three die [element 1202] above the interposer [element 1616], and the second semiconductor die is the middle element 1202, where the first and second semiconductor die overlap each other and the interposer element [element 1616]),
However, Jeng et al does not specifically disclose
[claim 10] a width of the interposer being greater than a sum of a width of the first dummy die, a width of the second dummy die, and a width of the second semiconductor die, the width of the interposer being greater than a width of the first semiconductor die.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified Jeng et al to extend the length of the interposer beyond the length of first and second dummy die and second semiconductor die in order to compensate for any extra length of the semiconductor die below the interposer and allow for extra structural stability and more electrical connections for the die.
Claim(s) 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Lee et al (US 20040140546).
Jeng et al teaches all of the limitations of the parent claim, claims 1 and 10, but does not specifically disclose,
[claim 5] The semiconductor package of claim 1, wherein each of the first dummy die and the second dummy die is a bulk metal block or a bulk silicon block.
[claim 16] The semiconductor package of claim 10, further comprising: a package substrate below the first semiconductor die; and a stiffener on the package substrate, wherein the stiffener surrounds the first semiconductor die, the interposer, the first dummy die, the second dummy die, and the second semiconductor die.
However, Lee et al teaches
[claim 5] The semiconductor package of claim 1, wherein each of the first dummy die and the second dummy die is a bulk metal block or a bulk silicon block (figure 6, paragraphs 0032-0033, where the multiple die can be metal block dummy dies).
[claim 16] The semiconductor package of claim 10, further comprising: a package substrate below the first semiconductor die; and a stiffener on the package substrate, wherein the stiffener surrounds the first semiconductor die, the interposer, the first dummy die, the second dummy die, and the second semiconductor die (figure 13, paragraph 0035, where element 50 is the stiffener, and element 12 is the package substrate, where the stiffener surrounds the entire device ontop of the package substrate, which read onto Elsherbini et al includes the first semiconductor device and the interposer, first and second dummy die and the second semiconductor die).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al to incorporate the teachings of Lee et al to incorporate dummy dies to allow for thermal optimization for high current and high heat semiconductor dies.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Oh (US 9299689).
Jeng et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 6] The semiconductor package of claim 1, further comprising: a first adhesive layer between the first dummy die and the interposer; and a second adhesive layer between the second dummy die and the interposer.
However, Oh does teach
[claim 6] The semiconductor package of claim 1, further comprising: a first adhesive layer between the first dummy die and the interposer; and a second adhesive layer between the second dummy die and the interposer (figure 9, col 3 lines 31-53, where element 410 on the left-hand side is the first dummy die, and element 410 on the right-hand side is the second dummy die [read into from Elsherbini], where element 430 is the adhesive layer between each dummy die and the interposer [element 200]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al with the teachings of Oh to use an adhesive material to connect the die to the interposer so that structural stability is maintained.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Choi (US 20210358866).
Jeng et al teaches all of the limitations of the parent claim, claim 8, but does not specifically disclose,
[claim 9] The semiconductor package of claim 8, wherein the width of the interposer is 1 mm to 90 mm greater than the width of the first semiconductor die.
However, Choi teaches
[claim 9] The semiconductor package of claim 8, wherein the width of the interposer is 1 mm to 90 mm greater than the width of the first semiconductor die (paragraphs 0044 and claim 10, where the width of the interposer is between 20 and 80 mm and the width of the first semiconductor die is between 1 mm and 10 mm, where the difference between the widths are between 19-79 mm which falls in the range of 1 mm to 90 mm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al to incorporate the teachings of Choi in order to have an interposer wider than the semiconductor chip to allow for connectivity to multiple devices improving efficiency [more width allows for greater amount of connections per unit area].
Claim(s) 11-13 and 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Yu et al (US 20220344287).
Jeng et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 11] The semiconductor package of claim 10, wherein the interposer includes a lower protection layer and a lower pad surrounded by the lower protection layer, the first semiconductor die includes an upper protection layer and an upper pad surrounded by the upper protection layer, the lower protection layer is in contact with the upper protection layer, and the lower pad is in contact with the upper pad.
[claim 12] The semiconductor package of claim 11, wherein the interposer includes: a lower wiring structure on the lower pad; a substrate on the lower wiring structure; and a through via that penetrates the substrate.
[claim 13] The semiconductor package of claim 12, wherein the lower wiring structure includes, a lower wiring dielectric layer between the lower protection layer and the substrate; and a lower conductive structure in the lower wiring dielectric layer, and the lower conductive structure electrically connects the lower pad to the through via.
[claim 17] The semiconductor package of claim 10, wherein the interposer includes an upper protection layer and an upper pad surrounded by the upper protection layer, the second semiconductor die includes a lower protection layer and a lower pad surrounded by the lower protection layer, the lower protection layer is in contact with the upper protection layer, and the lower pad is in contact with the upper pad.
However, Yu et al does teach
[claim 11] The semiconductor package of claim 10, wherein the interposer includes a lower protection layer and a lower pad surrounded by the lower protection layer (figure 1, paragraph 0018, where element 102 is the interposer and element 108 is the lower pad and element 110 surrounds the lower protection layer that surrounds the lower pad),
the first semiconductor die includes an upper protection layer and an upper pad surrounded by the upper protection layer (figure 1, paragraph 0018, where element 56 is the upper pad on the first semiconductor die [element 50C read onto the first semiconductor die from Elsherbini et al], and element 58 is the upper protective layer that surrounds element 56),
the lower protection layer is in contact with the upper protection layer, and the lower pad is in contact with the upper pad (figure 1, paragraph 0018, where element 56 [lower pad] is connected to element 108 [upper pad], and elements 58 [lower protection layer] and 110 [upper protection layer] are in contact).
[claim 12] The semiconductor package of claim 11, wherein the interposer includes: a lower wiring structure on the lower pad; a substrate on the lower wiring structure; and a through via that penetrates the substrate (figure 3, paragraphs 0027-0028, where element 102 is the interposer which includes a lower wiring structure [element 62] on the lower pad [element 108], and a substrate on the lower wiring structure [portion of element 102 over element 62] with through vias [element 104] through the substrate. Keep in mind figure 3 is flipped from the use of the structure of figure 1).
[claim 13] The semiconductor package of claim 12, wherein the lower wiring structure includes, a lower wiring dielectric layer between the lower protection layer and the substrate (figure 3, paragraphs 0027-0028, where element 62 is the lower wiring structure and includes a lower wiring dielectric layer between the lower protection layer and the substrate [element 60]),
and a lower conductive structure in the lower wiring dielectric layer, and the lower conductive structure electrically connects the lower pad to the through via (figure 3, paragraphs 0027-0028, where element 62 is the lower wiring structure and includes a conductive element, element 62, which connect the lower pad [element 108] to the through vias [element 104]).
[claim 17] The semiconductor package of claim 10, wherein the interposer includes an upper protection layer and an upper pad surrounded by the upper protection layer (figure 8, paragraph 0039, where element 114 is the upper pad on the interposer and element 116 is the upper protection layer surrounding the upper pad),
the second semiconductor die includes a lower protection layer and a lower pad surrounded by the lower protection layer (figure 9, paragraph 0042, where the second semiconductor die [element 150 in the middle] contains a lower pad and lower protection layer that is akin to element 56 [pad] and 58 [protection layer] of the first semiconductor die [element 50C] as described in paragraph 0042, and can be seen by the additional pad and protection layer on element 150 not present in figure 8 but is present in figure 9),
the lower protection layer is in contact with the upper protection layer, and the lower pad is in contact with the upper pad (figure 9, paragraph 0042, where the lower pad and protection layer of the second semiconductor die [middle element 150] is in contact with the upper pad and protection layer of the interposer [element 50C]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al with the teachings of Yu et al to connect the semiconductor die to the interposer with connection points and protection layers to allow for maximal efficiency by surrounding the connectors with protection layers and connecting them in direct contact.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Chen et al (US 20180374821).
Jeng et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose,
[claim 14] The semiconductor package of claim 10, wherein the second semiconductor die includes a plurality of second semiconductor dies, a top surface of an uppermost semiconductor die among the plurality of second semiconductor dies is coplanar with a top surface of the first dummy die and a top surface of the second dummy die.
However, Chen et al does teach
[claim 14] The semiconductor package of claim 10, wherein the second semiconductor die includes a plurality of second semiconductor dies (figure 1, paragraph 0021, where elements 111 and 102 are the two sets of dummy dies and the second semiconductor die, where element 111 contains a stack of semiconductor dies, per MPEP 2144.04, VI. Reversal, Duplication or Rearrangement of Parts, part C, where the rearrangement of parts is obvious to one of ordinary skill in the art as long as it does not change the functionality of the device, in the particular case, the rearrangement of on stack of die [element 111] and the middle die [element 102] would situate a stack of side in the place of the second semiconductor die of Elsherbini et al),
a top surface of an uppermost semiconductor die among the plurality of second semiconductor dies is coplanar with a to surface of the first dummy die and a top surface of the second dummy die (figure 1, paragraph 0021, where elements 111 and 102 are all coplanar with a top surface of one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al to incorporate the teachings of Yu et al in order to allow for stacked semiconductor die to replace the second semiconductor die in order to improve functionality of the device by allowing more die in a smaller space to function.
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Chung et al (US 20230005814).
Jeng et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 15] The semiconductor package of claim 10, wherein the first semiconductor die is a logic semiconductor die, and the second semiconductor die is a memory semiconductor die.
However, Chung et al does teach
[claim 15] The semiconductor package of claim 10, wherein the first semiconductor die is a logic semiconductor die, and the second semiconductor die is a memory semiconductor die (figure 1, paragraphs 0027-0028, where the first semiconductor die [element 100] is a logic die, and element 200 [second semiconductor chip] is a memory die).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al to incorporate the teachings of Chung et al in order to allow for a logic and memory die to be connected through an interposer to allow for a functional logic circuit by connecting it to a memory die.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20230133235).
Jeng et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 18] The semiconductor package of claim 10, wherein a height of the first dummy die and a height of the second dummy die are greater than a height of the second semiconductor die.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Elsherbini to adjust the heights of each semiconductor die for specific use case needs, increasing the functionality over the overall device.
Claim(s) 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610) in view of Elsherbini et al (US 20230133235) and in further view of Lee et al (US 20150214191 A1).
Jeng et al teaches
[claim 19] A semiconductor package, comprising: a package substrate; a stiffener in contact with the package substrate (figure 22, paragraph 0069 and 0095, where element 2202 is the stiffener [portion between elements 2106 and 1312] is in contact with the package substrate [element 112]);
a first semiconductor die over the package substrate; an interposer over the first semiconductor die, the stiffener separated from and below the interposer, and laterally separated from the first semiconductor die (figure 22, paragraphs 0054 and 0095, where element 1312 in the middle is the first semiconductor die over the package substrate [element 112], an interposer [element 1616] over the first semiconductor die, and the stiffener separated below the interposer and around the first semiconductor die [element 2202 between elements 2106 and 1312 surrounds element 1312 and is below element 1616]);
a first molding layer surrounding the first semiconductor die (figure 22, paragraph 0095, where element 2202 between elements 1410 and 2106 is the first molding layer and surrounds the first semiconductor die);
However, Jeng et al does not specifically disclose
[claim 19] a first dummy die, a second dummy die, a third dummy die, a fourth dummy die, and a plurality of second semiconductor dies over the interposer;
and a second molding layer surrounding the first to fourth dummy dies and the second semiconductor dies, the second semiconductor dies between the first and second dummy dies, and the first and second dummy dies and the second semiconductor dies between the third and fourth dummy dies.
However, Elsherbini et al teaches
a first dummy die, a second dummy die, a third dummy die, a fourth dummy die, and a second semiconductor die over the interposer (figure 5, paragraph 0065, where element 114-3 is the first dummy die, element 114-13 is the second dummy die, element 114-11 is the third dummy die, and element 114-10 is the fourth dummy die, all over the interposer [element 148]);
and a second molding layer surrounding the first to fourth dummy dies and the second semiconductor die (figure 5, paragraph 0062, where element 432 [shown in figure 4] above the interposer [element 148] surrounds the first through fourth dummy die and the second semiconductor die),
the second semiconductor die between the first and second dummy dies, and the first and second dummy dies and the second semiconductor dies between the third and fourth dummy dies (figure 5, paragraph 0065, where element 114-12 is the second semiconductor die and is located on a diagonal plane between the first and second dummy dies [elements 114-3 and 114-13] and the first and second dummy dies and the second semiconductor die also lie between the third and fourth dummy dies [elements 114-11 and 114-10] on a diagonal line).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al to incorporate the teachings of Elsherbini et al to incorporate multiple die above the interposer to maximize density of die in a specific package.
However, Jeng et al as modified does not specifically disclose
[claim 19] a plurality of second semiconductor dies.
However, Lee et al does teach
[claim 19] a plurality of second semiconductor dies (figure 13, paragraph 0025, where element 10 contains a plurality of semiconductor die and are in place of element 114-12 of Elsherbini et al, where the singular semiconductor die is located).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al as modified to incorporate the teachings of Lee et al to include a stiffener with multiple semiconductor die to allow for greater package stability and efficiency by putting more die in a small space [more function per unit area] as well as protecting such die more efficiently, yielding greater durability.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al (US 20140217610), Elsherbini et al (US 20230133235), Lee et al (US 20150214191 A1) and in further view of Hsieh et al (US 20230011493).
Jeng et al as modified teaches all of the limitations of the parent claim, claim 19, but does not specifically disclose
[claim 20] The semiconductor package of claim 19, wherein the stiffener overlaps the first to fourth dummy dies, and the stiffener does not overlay any of the first semiconductor die and the second semiconductor dies (figure 2A, paragraphs 0060-0061, where elements 230a, 230a2, 230b, and 230b comprise the package stiffener [read onto from Jeng et al], and overlays only elements 123 and 125 over the interposer [element 122], where elements 123 and 125 are in the same location as the first through fourth dummy dies of Elsherbini et al, and element 124 is the in the same location as the second semiconductor die, where element 110 is the package substrate, thus the first semiconductor die is read onto the device [element 120] in totality which includes the first semiconductor die directly beneath the second semiconductor die [element 124 in Hsieh et al, figure 2A]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Jeng et al as modified to incorporate the teachings of Hsieh et al to protect the package with the stifferner on the the sides to allow for greater durability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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