DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the semiconductor layer". There is insufficient antecedent basis for this limitation in the claim. The claimed “semiconductor layer” is different from the claimed “doped semiconductor layer”. It appears that claim 8 is intended to be amended in the same way as claim 1 and the application will be examined as such; that is, as “…the insulating layer is interposed between the doped semiconductor layer and a semiconductor layer, the doped semiconductor layer comprising a semiconductor material of the semiconductor layer….” (emphasis added).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1, 4, 5, 7, 8, 9, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukuzumi et al. (US Pub. 2016/0079164).
Regarding independent claim 1, Fukuzumi teaches a three-dimensional (3D) semiconductor device (Figs. 4, 6; para. 0025+), comprising: a first semiconductor structure (W1) comprising a first device layer (all layers below the BG of W1), a doped semiconductor layer (BG; para. 0026), and an insulating layer (45/48; para. 0027), the first device layer comprising a memory stack (WL/40) (Fig. 4; para. 0024),
wherein:
the memory stack and the insulating layer are arranged at opposite sides of the doped semiconductor layer (Fig. 6), and the doped semiconductor layer extends continuously, in a lateral direction, over the memory stack to a region outside a staircase portion of the memory stack (Fig. 6);
the doped semiconductor layer is located between the first device layer and the insulating layer, and the doped semiconductor layer is in direct contact with the insulating layer (Figs. 4, 6);
the insulating layer is interposed between the doped semiconductor layer and a semiconductor layer (10) (Fig. 6; para. 0083); the doped semiconductor layer comprising a semiconductor material of the semiconductor layer (i.e. silicon; para. 0026, para. 0083) doped with a first dopant (boron; para. 0026), and the insulating layer comprising the same semiconductor material of the semiconductor layer (i.e. silicon) doped with a second dopant that is different from the first dopant; and the second dopant comprises oxygen (para. 0027 teaching the insulating layer comprises silicon oxide).
Re claim 4, Fukuzumi teaches the memory stack comprises a plurality of conductive layers (WL) and dielectric layers (40) (para. 0024); and
the first device layer further comprises a channel structure (20) extending through the memory stack and into the doped semiconductor layer (Fig. 4; para. 0035).
Re claim 5, Fukuzumi teaches a second semiconductor structure (W1) comprising a second device layer (all layers between 5 and 94 of W2) and a second substrate (5), wherein the second semiconductor structure is bonded with the first semiconductor structure (para. 0025).
Re claim 6, Fukuzumi teaches wherein the channel structure comprises a semiconductor channel in contact with the doped semiconductor layer (Fig. 4). Please note that generally speaking, “in contact” is interpreted to include layers in between while “in direct contact” in generally considered to be interpreted without layers in between.
Re claim 7, Fukuzumi teaches wherein the insulating layer comprises a silicon oxide (para. 0027).
Regarding independent claim 8, Fukuzumi teaches a three-dimensional (3D) semiconductor device (Figs. 4, 6; para. 0025+), comprising: a first semiconductor structure (W1) comprising a first device layer (all layers below the BG of W1) and an insulating layer (45/48; para. 0027), wherein:
the first device layer comprises a memory stack (WL/40) (Fig. 4; para. 0024), and the memory stack and the insulating layer are arranged at opposite sides of a doped semiconductor layer (BG; para. 0026), the doped semiconductor layer extending continuously, in a lateral direction, over the memory stack to a region outside a staircase portion of the memory stack (Fig. 6);
the doped semiconductor layer is in direct contact with the insulating layer (Fig. 6); and
the insulating layer is interposed between the doped semiconductor layer and a semiconductor layer (10; para. 0083), the doped semiconductor layer comprising a semiconductor material of the semiconductor layer (i.e. silicon; para. 0026, para. 0083) doped with a first dopant (boron; para. 0026), and the insulating layer comprising the same semiconductor material of the semiconductor layer (i.e. silicon) doped with a second dopant that is different from the first dopant; and the second dopant comprises oxygen (para. 0027 teaching the insulating layer comprises silicon oxide);
a second semiconductor structure (W2) comprising a second device layer (all layers between 5 and 94) and a second substrate (5), wherein:
the first semiconductor structure is bonded with the second semiconductor structure (para. 0025).
Re claim 9, Fukuzumi teaches wherein the insulating layer is on the doped semiconductor layer, and the doped semiconductor layer is located between the memory stack and the insulating layer (Fig. 6).
Re claim 12, Fukuzumi teaches wherein: the memory stack comprises a plurality of conductive layers (WL) and dielectric layers (40) (para. 0024); and
the first device layer further comprises a channel structure (20) extending through the memory stack and into the doped semiconductor layer (Fig. 4; para. 0035).
Re claim 13, Fukuzumi teaches wherein the insulating layer comprises a silicon oxide layer (para. 0027).
Claim(s) 1 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US Pub. 2018/0358371).
Regarding independent claim 1, Hwang teaches a three-dimensional (3D) semiconductor device (Fig. 15; para. 0089+), comprising: a first semiconductor structure (C2) comprising a first device layer (all layers below 10S), a doped semiconductor layer (10S; para. 0090, para. 0041), and an insulating layer (184; para. 0090), the first device layer comprising a memory stack (GP/120; para. 0044),
wherein:
the memory stack and the insulating layer are arranged at opposite sides of the doped semiconductor layer (Fig. 15), and the doped semiconductor layer extends continuously, in a lateral direction, over the memory stack to a region outside a staircase portion of the memory stack (Fig. 15);
the doped semiconductor layer is located between the first device layer and the insulating layer, and the doped semiconductor layer is in direct contact with the insulating layer (Fig. 15);
the insulating layer is interposed between the doped semiconductor layer and a semiconductor layer (10F) (Fig. 15); the doped semiconductor layer comprising a semiconductor material of the semiconductor layer (i.e. silicon; para. 0041) doped with a first dopant (for example, p-type (para. 0041), and the insulating layer comprising the same semiconductor material of the semiconductor layer (i.e. silicon) doped with a second dopant that is different from the first dopant; and the second dopant comprises oxygen (para. 0090 teaching the insulating layer comprises silicon oxide).
Re claim 21, Hwang teaches wherein: the first device layer further comprises a channel structure (CP) extending through the memory stack (para. 0051); and
the channel structure comprises a semiconductor channel, and an end of the semiconductor channel is in direct contact with the doped semiconductor layer to have an electrical connection with the doped semiconductor layer (Figs. 3A, 3B; para. 0054-0055).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi et al. (US Pub. 2016/0079164) in view of Komori et al. (US Pub. 2012/0211820) and Faul (US Pub. 2016/0379993).
Re claims 2, 3, 10, and 11, Fukuzumi teaches wherein the doped semiconductor layer (which is acting as the back gate of the device) comprises silicon (para. 0026) or polysilicon (para. 0108) doped with; for example, boron (a p-type dopant) (para. 0026).
Fukuzumi is silent with respect to wherein the BG could instead be doped with an n-type dopant.
Komori teaches 3D semiconductor device wherein the back gate comprises silicon doped with; for example, phosphorous (an n-type dopant) (para. 0025).
It would have been obvious to one of ordinary skill in the art at the time of filing that the p-type doping of Fukuzumi could be substituted with the n-type doping of Komori with a reasonable expectation of success as either dopant type would impart conductivity to the semiconductor layer. Furthermore, choosing n-type based devices vs p-type based devices and vice-versa is basic knowledge in the art and choosing one over the other would have been an obvious matter of engineering choice (as evidenced by Faul para. 0054).
Response to Arguments
The Examiner agrees the current amendments overcome the Lee reference; however, upon further review, the Examiner finds that they do not overcome the Fukuzumi.
Applicant argues Fukuzumi teaches the insulating film are formed of base layers having different compositions.
The patentability of device claims is based on the product itself and not based on the process of forming the device (MPEP 2113). That is, whether the insulating layer of claim 1 is made through implanting a dopant into a semiconductor layer as Applicant does or whether the dielectric layer is formed by another method such as deposition is inconsequential to determining the patentability of the device. Because the product of Fukuzumi is the same structure as the claimed device, Fukuzumi is considered to read on the claim.
Using different words, the disputed limitation is a doped semiconductor layer/insulating layer/semiconductor layer stack wherein each layer comprises a same semiconductor material (silicon, in the case of Fukuzumi and newly cited Hwang) and wherein the doped semiconductor layer and the insulating layer are doped with different dopants, wherein the “dopant” of the insulating layer comprises oxygen. When the insulating layer comprises silicon oxide (as is the case in Fukuzumi and Hwang; refer also claims 7, 13) and when the dopants of the doped semiconductor layer are n-type or p-type dopants (as is the case in Fukuzumi and Hwang) then the claim is considered to be met because the structure of the claim and the reference is the same, even if formed differently.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899