DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claim 1 is rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1
4. Regarding Claim 1, Z1 discloses a semiconductor device (see in particular Fig. 5) comprising:
a semiconductor module (structure below element 10) including a semiconductor chip (element 33 and see pg. 8 “the first power chip 22, the second power chip 23, the third power chip 32 and the fourth power chip 33 comprises a plurality of parallel semiconductor chip. wherein the number of the parallel semiconductor chips of each power chip can be set according to the actual power requirement”) in which a semiconductor element (element 32) is disposed;
a wiring substrate (element 21, see pg. 8 “the first phase power output terminal 26 through the load is electrically connected with the first phase power output terminal 36”) electrically connected to the semiconductor module;
a sealing member (element 80, see pg. 7 “packaging layer 80”) sealing the semiconductor module and the wiring substrate (see Fig. 5); and
a thermal diffusion plate (element 10, see pg. 7 “first radiating plate 10 comprises a radiating metal plate”) disposed between the semiconductor module and the wiring substrate (see Fig. 5), and having a thermal conductivity higher than a thermal conductivity of the sealing member (metal has a higher thermal conductivity than the dielectric packaging layer), wherein
the thermal diffusion plate has a plate shape and is disposed in the sealing member in a state where a plane direction of the thermal diffusion plate is along a direction intersecting an arrangement direction of the semiconductor module and the wiring substrate (see Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 2 is rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Yoon et al. (US 2019/0103425 A1), hereinafter as Y1
6. Regarding Claim 2, Z1 discloses the semiconductor device according to claim 1, wherein
the sealing member includes a first sealing member (portion below element 10) that seals the semiconductor module and a second sealing member (portion above element 10) that seals the wiring substrate.
Z1 does not explicitly disclose the first sealing member and the second sealing member are bonded to each other via a bonding layer.
Y1 discloses the first sealing member and the second sealing member are bonded to each other via a bonding layer (see Fig. 7B element 120 and 220 bonded via a bonding layer element 195,295, see [0109] “interlayer insulating layer 120 … interlayer insulating layer 220 … bonding layers 195 and 295”).
The bonding layer between the sealing members as taught by Y1 is incorporated as a bonding layer between the sealing members of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with Z1 because the combination allows for simple pressure bonding for mechanical attachment between sealing members (see Y1 [0132] “when the first and second bonding layers 195 and 295 are formed of the same materials, the first and second bonding layers 195 and 295 may be bonded by pressure without a separate bonding layer”); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sealing member interface for another to obtain predictable results (see Y1 Fig. 8).
7. Claims 3 are rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Shikano (US 2014/0054751 A1), hereinafter as S1
8. Regarding Claim 3, Z1 discloses the semiconductor device according to claim 1, wherein the semiconductor module and the wiring substrate are mechanically connected to each other (see Fig. 5), and
the sealing member seals the semiconductor module and the wiring substrate (see Fig. 5)
Z1 does not explicitly disclose a support portion, and the sealing member integrally seals.
S1 discloses a support portion, and the sealing member integrally seals (see Figs. 1, 10-11 support portion element 11, and the sealing member element 7 of the elements 1 are integral, see [0033] “electrode 11” and [0029] “resin 7”).
The support portion and integral sealing member as taught by S1 is incorporated as a support portion and integral sealing member of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with Z1 because the combination allows for electrical and mechanical support and connection to external sources and secure electrical creepage and spatial distances (see S1 [0033]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sealing member interface and wiring connection implementation for another to obtain predictable results (see S1 Figs. 10-11).
9. Regarding Claim 8, Z1 discloses the semiconductor device according to claim 1.
Z1 does not explicitly disclose wherein the thermal diffusion plate is disposed in a state where a part of the thermal diffusion plate protrudes from the sealing member.
S1 discloses wherein the thermal diffusion plate is disposed in a state where a part of the thermal diffusion plate protrudes from the sealing member (see Figs. 1,14 element 13 protrudes from sealing member elements 7 of elements 1, see [0035] “radiator fin 13”).
The protruding extension shape of the thermal diffusion plate as taught by S1 is incorporated as a protruding extension shape of the thermal diffusion plate of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with Z1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known extending length of the thermal diffusion plate with respect to the sealing member for another to obtain predictable results (see S1 Fig. 14).
10. Regarding Claim 9, Z1,S1 disclose the semiconductor device according to claim 8, wherein (see Z1 Fig. 5 and S1 Fig. 14)
the semiconductor module further includes a connection terminal (see S1 element 11 and [0035] “electrodes 11”) that is connected to the semiconductor chip (see S1 [0035]),
a part of the connection terminal protrudes from the sealing member (see S1 Fig. 14), and
the thermal diffusion plate and the connection terminal protrude from different surfaces of the sealing member (see S1 Fig. 14 side versus top surface protrusions).
The connection terminal as taught by S1 is incorporated as the connection terminal of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with Z1 because the combination allows for electrical and mechanical support and connection to external sources and secure electrical creepage and spatial distances (see S1 [0033]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sealing member interface and wiring connection implementation for another to obtain predictable results (see S1 Figs. 10-11).
11. Regarding Claim 10, Z1 discloses the semiconductor device according to claim 1.
Z1 does not explicitly disclose wherein the thermal diffusion plate is insulated from the semiconductor chip and the wiring substrate.
S1 discloses wherein the thermal diffusion plate is insulated from the semiconductor chip and the wiring substrate (see Fig. 14 elements 10, 12 – element 10 can be seen labeled in Figs. 1,3 – insulate the thermal diffusion plate from the semiconductor chip, see [0024] “insulating material 10”, [0025] “The insulating material 10 is disposed under the through hole 8 to insulate the electrode 11 from the heat spreader 12” The electrical connection among active components occurs through the electrode elements 11).
The thermal diffusion plate insulated configuration with electrode terminals for conductive connections among active components as taught by S1 is incorporated as the thermal diffusion plate insulated configuration with electrode terminals for conductive connections among active components of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with Z1 because the combination allows for electrical and mechanical support and connection to external sources and secure electrical creepage and spatial distances (see S1 [0033]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sealing member interface and wiring connection implementation for another to obtain predictable results (see S1 Figs. 10-11).
12. Regarding Claim 11, Z1 discloses the semiconductor device according to claim 1, wherein
the semiconductor module includes a coupling member (wire bond connected to the semiconductor chip) and a connection terminal (elements 312,34, see pg. 5 “electrode portion 312 … input terminal 34”),
the coupling member is connected to a surface of the semiconductor chip that faces the wiring substrate (see Fig. 5), and
the coupling member has a protruding portion that protrudes from the semiconductor chip in a normal direction (see Fig. 5 portion of element 312 directly contacting the semiconductor chip in a normal direction),
the connection terminal is connected to the protruding portion of the connection terminal (see Fig. 5), and
the thermal diffusion plate is configured by the connection terminal (see Fig. 5).
Z1 does not disclose the connection terminal has a portion facing the semiconductor chip in the arrangement direction of the semiconductor module and the wiring substrate
S1 discloses (see Fig. 14) the connection terminal (element 11, see [0033] “electrode 11”) has a portion facing the semiconductor chip (element 3, see [0023] “semiconductor chip 3” labeled in Fig. 1) in the arrangement direction of the semiconductor module and the wiring substrate (vertically stacked direction).
The connection terminal and orientation as taught by S1 is incorporated as a connection terminal and orientation of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with Z1 because the combination allows for electrical and mechanical support and connection to external sources and secure electrical creepage and spatial distances (see S1 [0033]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known sealing member interface and wiring connection implementation for another to obtain predictable results (see S1 Figs. 10-11).
13. Regarding Claim 12, Z1, S1 disclose the semiconductor device according to claim 11,
wherein the semiconductor module further includes a support substrate (see Z1 element 31) to which the semiconductor chip is disposed (see Z1 Fig. 5), and
the connection terminal is thermally connected to the support substrate (see Z1 Fig. 5).
14. Claim 4 is rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Minamio et al. (US 2013/0015567 A1), hereinafter as M1
15. Regarding Claim 4, Z1 discloses the semiconductor device according to claim 1, wherein an area of a surface of the thermal diffusion plate that intersects the arrangement direction of the semiconductor module and the wiring substrate more than an area of a surface of the semiconductor chip that intersects the arrangement direction of the semiconductor module and the wiring substrate (see Fig. 5)
Z1 does not disclose the area is twice or more.
M1 discloses wherein an area of a surface of the thermal diffusion plate that intersects the arrangement direction is twice or more of an area of a surface of the semiconductor chip that intersects the arrangement direction (see Figs. 12-14 the area of the thermal diffusion plate element 3 filling the area within the outer package element 4 spans across a plurality of power and control elements T1,T2, etc. comprising semiconductor chips such that the area of element 3 is more than twice the area of a chip, see [0034] “power element T1 which is an example of a first semiconductor chip, a first lead frame 1 with the power element 1 fixed thereto, a control element T2 which is an example of a second semiconductor chip … heat dissipation plate 3 … outer package 4”).
The area of the thermal diffusion plate relationship with the semiconductor chips as taught by M1 is incorporated as an area of the thermal diffusion plate relationship with the semiconductor chips of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of M1 with Z1 because the combination allows for incorporation of a plurality of semiconductor chips within the outer package (see M1 Figs. 12-14); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known area of a thermal diffusion plate with semiconductor chips for another to obtain predictable results (see M1 Figs. 12-14).
16. Claim 5 is rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Kodaira et al. (US 2023/0345637 A1), hereinafter as K1
[Shimuta (US 2020/0271824 A1), hereinafter as S2, is utilized herein as evidence]
17. Regarding Claim 5, Z1 discloses the semiconductor device according to claim 1, wherein
the thermal diffusion plate is made of a material having a thermal conductivity that is greater than a thermal conductivity of the sealing member (the thermal diffusion plate is metal which has a higher thermal conductivity than the dielectric packaging sealing member).
Z1 does not disclose ten times or more of the thermal conductivity of the sealing member
K1 discloses the thermal diffusion plate material can be aluminum, iron, silver, copper, or an alloy (see [0027]) and the sealing member can be epoxy resin, phenolic resin, maleimide resin with optional fillers (see [0022]).
The material of the thermal diffusion plate and sealing member as taught by K1 is incorporated as a material of the thermal diffusion plate and sealing member of Z1, wherein the combination discloses ten times or more of the thermal conductivity of the sealing member (see evidentiary reference S2 [0030] “thermal conductivity of metal such as copper, aluminum or the like is about 100 [W/m/K] or more, whereas thermal conductivity of plastics such as a polypropylene resin, a polyethylene resin, an acrylic resin, a polycarbonate resin, an epoxy resin or the like is about 0.1 to 0.5 [W/m/K], and is about 1000 times smaller”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with Z1 because the combination provides superior thermal conductivity heat dissipation and sealing material for mechanical and electrical protection (see K1 [0027, 0022]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known heat dissipation and sealing member material for another to obtain predictable results (see K1 [0027, 0022]).
18. Claim 6 is rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Denta et al. (US 2012/0066258 A1), hereinafter as D1
19. Regarding Claim 6, Z1 discloses the semiconductor device according to claim 1.
Z1 does not explicitly disclose wherein the thermal diffusion plate has a thickness of 1 mm or less along the arrangement direction of the semiconductor module and the wiring substrate.
D1 discloses wherein the thermal diffusion plate has a thickness of 1 mm or less along the arrangement direction of the semiconductor module and the wiring substrate (see [0023] “the thickness of the heat dissipating plate 25 is preferably at least 0.1 mm but not greater than 2.0 mm”; See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The thickness of the thermal diffusion plate as taught by D1 is incorporated as a thickness of the thermal diffusion plate of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of D1 with Z1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known thermal diffusion plate thickness for another in a similar device to obtain predictable results (see D1 [0023])
20. Claim 7 is rejected under 35 U.S.C. 103 as obvious over Zhong et al. (CN 115148701 A, see attached translation document), hereinafter as Z1, in view of Lee (US 2024/0021591 A1), hereinafter as L1
21. Regarding Claim 7, Z1 discloses the semiconductor device according to claim 1, the thickness direction of the thermal diffusion plate is a direction along the arrangement direction of the semiconductor element and the wiring substrate (see Fig. 5).
Z1 does not explicitly disclose wherein the thermal diffusion plate is made of a material whose thermal conductivity is higher in the plane direction than in a thickness direction of the thermal diffusion plate.
L1 discloses wherein the thermal diffusion plate is made of a material whose thermal conductivity is higher in the plane direction than in a thickness direction of the thermal diffusion plate (see [0097] “the heat transfer unit 70 may include a metal or a metal alloy including gold (Au), silver (Ag), copper (Cu), iron (Fe), or the like, or a conductive material such as graphite, graphene, and the like”; the material of the thermal diffusion plate is selected as graphite which is a same material as the Applicant’s invention which inherently results in the claimed feature).
The graphite material of the thermal diffusion plate as taught by L1 is incorporated as the graphite material of the thermal diffusion plate of Z1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with Z1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known thermal diffusion plate material for another in a similar device to obtain predictable results (see Z1 [0097])
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818
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