DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 07/13/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishige (US 20160163272 A1) in view of Xiong (US 10481454 B1).
Regarding claim 1, Ishige discloses an array substrate (Fig. 1, BS) comprising: a plurality of signal lines (SL) provided in an active area (DP(DPA)); and a switch circuit (comprises all instances of SWS shown in Fig. 4) provided in a surrounding area (Shown in Fig. 4) around the active area and connected to the signal lines (Shown according to Applicant's Fig. 1), wherein the signal lines include a first signal line (Leftmost SL1) and a second signal line (leftmost SL2), the switch circuit includes: a circuit unit (Components of SWS) including a first transistor (Tr1) and a second transistor (Tr2); a first input line (line between CS and leftmost SWS; SL in Fig. 5) connected to the first transistor (Figs. 4-5 show first input line connected to Tr1) and the second transistor (Figs. 4-5 show first input line connected to Tr2); a first select line (comprises SEL1, GLs(SEL1) as shown in Fig. 5, and GEs as shown in Fig. 6) which is provided between the circuit unit and the active area (Fig. 6 shows GLs portion of first select line being between the circuit unit comprising Tr1 and active area DPA) and supplies a first select signal for turning the first transistor on (Para. 88 "The transistor Tr1 is controlled to be switched on and off by the switching signal SEL1"); a second select line (comprises SEL2, GLs(SEL2) as shown in Fig. 5, and GEs as shown in Fig. 6) which supplies a second select signal for turning the second transistor on (Para. 88 "the transistor Tr2 is controlled to be switched on and off by the switching signal SEL2"); a first output line which connects the first transistor and the first signal line to each other (portion of line connected Tr1 to leftmost SL1,
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also shown in Fig. 5 as portion of leftmost SL connecting leftmost Tr1 to lower GLs) and intersects with the first select line (Shown in Fig. 6); and a second output line which connects the second transistor and the second signal line to each other (portion of line connecting Tr2 to leftmost SL2, also shown in Fig. 5 as portion of leftmost SL connecting leftmost Tr1 to lower GLs) and a first intersection of the first output line which intersects with the first select line and a second intersection (see attached figure). However, Ishige does not disclose the second output line intersecting with the first select line and the first and second intersections being formed in different layers.
On the other hand, Xiong discloses a circuit arrangement in which select lines (Fig. 2, 10) intersects with various signal lines (D1, L1) in different layers. It would have been obvious to one of ordinary skill in the art to modify Ishige according to the teachings of Xiong such that the second output line would be formed in a different layer than the first output line and therefore the first and second intersections would be formed in different layers, in order to reduce the overall footprint of the device and allow for a higher pixel density by vertically overlapping wiring routes.
Regarding claim 3, Ishige discloses wherein the first transistor includes: a first semiconductor layer (Fig. 7, CHs(SCs)); a first gate electrode (GEs) which is connected to the first select line (Fig. 6 shows GEs connected to first select line indicated by lower GLs) and intersects with the first semiconductor layer (Fig. 7 shows GEs intersecting with CHs(SCs) in accordance with Applicant's Fig. 9); a first source electrode (SEs) which connects the first input line and the first semiconductor layer to each other (Fig. 6 shows SL of Tr1 connecting to CHs); and a first drain electrode (DEs) which connects the first semiconductor layer and the first output line to each other (Fig. 6 shows DEs of Tr1 connecting CHs to leftmost SL1 through first output line), and the first intersection is formed in a same layer as the first gate electrode (Fig. 6 shows GEs and GLs formed of on piece, so GEs is necessarily formed in the same layer as the intersection between the first output line and GLs).
Regarding claim 8, Ishige discloses wherein the first transistor and the second transistor are arranged in an extension direction of the signal lines (Fig. 6 show Tr1 and Tr2 extending from the signal lines SL).
Regarding claim 9, Ishige discloses wherein the signal lines further include a third signal line (Fig. 4, SL1 in middle SWS) and a fourth signal line (SL2 in middle SWS), the circuit unit further includes: a third transistor (rightmost transistor Tr1 in middle SWS) to which the first select signal is supplied from the first select line (Shown); and a fourth transistor (middle transistor TR2 in middle SWS) to which the second select signal is supplied from the second select line (Shown), the switch circuit further includes: a second input line (line between CS and middle SWS; rightmost SL in Fig. 5) connected to the third
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transistor and the fourth transistor (Shown); a third output line which connects the third transistor and the third signal line to each other (Fig. 4, portion of line connecting Tr1 in middle SWS to SL1 extending from middle SWS) and intersects with the first select line (Shown in Fig. 6); and a fourth output line which connects the fourth transistor and the fourth signal line to each other (Fig. 4, portion of line connecting Tr2 in middle SWS to SL2 extending from middle SWS) and a third intersection of the third output line which intersects with the first select line and a fourth intersection (see attached figure). However, Ishige does not disclose the fourth output line intersecting with the first select line and the third and fourth intersections being formed in different layers.
On the other hand, Xiong discloses a circuit arrangement in which select lines (Fig. 2, 10) intersects with various signal lines (D1, L1) in different layers. It would have been obvious to one of ordinary skill in the art to modify Ishige according to the teachings of Xiong such that the fourth output line would be formed in a different layer than the third output line and therefore the third and fourth intersections would be formed in different layers, in order to reduce the overall footprint of the device and allow for a higher pixel density by vertically overlapping wiring routes.
Regarding claim 10, Ishige discloses wherein the first transistor, the second transistor, the third transistor and the fourth transistor are arranged in an extension direction of the signal lines (Fig. 4 shows first, second, third, and fourth transistors extending in the Y direction corresponding to the extension direction of the signal lines).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishige (US 20160163272 A1) in view of Xiong (US 10481454 B1) as applied to claims 1, 3, and 8-10 above, and further in view of Han (US 20150185572 A1).
Regarding claim 4, Ishige in view of Xiong discloses the array substrate of claim 3. However, Ishige in view of Xiong does not disclose wherein the first select line includes a first layer formed in a same layer as the signal lines, and a second layer formed in a same layer as the first drain electrode.
On the other hand, Han discloses a select line (Fig. 5, comprises 221, 222 and their intermediate interconnects) including a first layer (221) and a second layer (222). It would have been obvious to one of ordinary skill in the art to modify Ishige in view of Xiong according to the teachings of Han such that the first layer would be formed in a same layer as any of the signal lines and a second layer would be formed in a same layer as the first drain electrode or any other layer besides the layer of the signal layers in order to reduce the impedance of select lines by forming multiple parallel connections to carry the select line signal.
Allowable Subject Matter
Claims 2 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record does not disclose the array substrate of claim 1, wherein the first select line is located between the first intersection and the second intersection in a thickness direction of the array substrate.
Regarding claim 5, the prior art of record does not disclose the array substrate of claim 1, further comprising an insulating layer located above the first transistor, the second transistor and the first select line, and formed of an organic material, wherein the second intersection is formed above the insulating layer. Specifically, the prior art of record fails to disclose the insulating layer being above the first select line, wherein the second intersection is formed above the insulating layer.
For this reason, claims 6-7 are also objected to as dependents of claim 5 and would be allowable if claim 5 were rewritten in independent form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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