DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/3/2024 and 12/4/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. US Pat 10,374,009. Regarding claim 1, Cheng teaches a memory device (fig. 2) (col.4, line 15) comprising: a first electrode (12, fig. 2) (col.4, line 18); a second electrode (11, fig. 2) (col.4, line 18) apart from and facing the first electrode (12); and a memory layer (10, fig. 2) (col.4, line 16) between the first electrode (12) and the second electrode (11), wherein the memory layer (10) has Ovonic threshold switching characteristics (col.3, line 65), the memory layer (10) is configured to have a threshold voltage of the memory layer (10) be changed as a density of active traps in the memory layer (10) is changed according to a polarity of and an intensity of a bias voltage applied to the memory layer (10), and an element composition (AsSeGe, fig. 1-2) (col.3, lines 64-65) distribution is configured to be maintained constant in the memory layer (10) in response to the threshold voltage of the memory layer (10) being changed (Cheng et al., fig. 1-2, col.3, lines 3-9). The memory layer (10) is considered to have the characteristics wherein “the memory layer is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed according to a polarity of and an intensity of a bias voltage applied to the memory layer, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer (10) being changed” because the memory layer (10) is made of (AsSeGe, fig. 1-2) (col.3, lines 64-65) in similar composition (fig. 1, col.3, lines 3-9) as that of the invention (see GeAsSe in fig. 12, [0074] of the specification of the instant application that has the claimed characteristics [0041]). It has been held that where the claimed and the prior art products are identical or substantially identical in structure or composition (as in this case), or produced by identical processes or substantially processes, a prima facie case of either anticipation or obviousness has been established. Since the composition of the memory layer of Cheng is the same as that of the invention, the product (memory layer) of Cheng must necessarily exhibit the properties as that of the invention – the properties being that “the memory layer is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed according to a polarity of and an intensity of a bias voltage applied to the memory layer, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer (10) being changed.” See MPEP 2112.01. Regarding claim 2, Cheng teaches the memory device of claim 1, wherein the memory layer (10) is configured to be in any one of a first state (off state, (col.2, lines 33-34)) having a first threshold voltage (low, (col.2, lines 33-34)) or a second state having a second threshold voltage (high threshold voltage, (col.2, lines 35-37)) greater than the first threshold voltage (low) (Cheng et al., (col.2, lines 33-37)).
Regarding claim 3, Cheng teaches the memory device of claim 2, wherein the memory layer (10) comprises a first region (bottom portion of 10, fig. 2) adjacent to the first electrode (12) and a second region (top portion of 10, fig. 2) adjacent to the second electrode (11) (Cheng et al., fig. 2).
Regarding claim 12, Cheng teaches the memory device of claim 2, wherein the memory device (fig. 2) is configured to operate such that in a read operation, a read voltage between the first threshold voltage and the second threshold voltage is applied to the memory layer (Cheng et al., col.9, lines 33-44).
Regarding claim 14, Cheng teaches the memory device of claim 3, wherein the memory layer (10) comprises a single layer comprising GeAsSe (AsSeGe, fig. 1-2) (col.3, lines 64-65), and in the memory layer (10), an atomic percent of germanium (Ge) is about 10 at % or more and about 30 at % or less (10-25 at%, fig. 1, col.3, lines 3-9), an atomic percent of arsenic (As) is about 10 at % or more and about 50 at % or less (15-46 at %, fig. 1, col.3, lines 3-9), and an atomic percent of selenium (Se) is about 40 at % or more and about 80 at % or less (27-60 at%, fig. 1, col.3, lines 3-9) (Cheng et al., fig. 1, (col.3, lines 3-9)).
Regarding claim 15, Cheng teaches the memory device of claim 14, wherein in response to the memory layer (10 made of AsSeGe) being changed from the first state to the second state or from the second state to the first state, the memory device is configured such that a ratio of Ge, As, and Se is maintained constant in the first region and the second region of the memory layer(Cheng et al., fig. 1, (col.3, lines 3-9)). The memory layer (10) is considered to have the characteristics “wherein in response to the memory layer being changed from the first state to the second state or from the second state to the first state, the memory device is configured such that a ratio of Ge, As, and Se is maintained constant in the first region and the second region of the memory layer” because the memory layer (10) is made of (AsSeGe, fig. 1-2) (col.3, lines 64-65) in similar composition (fig. 1, col.3, lines 3-9) as that of the invention (see GeAsSe in fig. 12, [0074] of the specification of the instant application that has the claimed characteristics [0041]). It has been held that where the claimed and the prior art products are identical or substantially identical in structure or composition (as in this case), or produced by identical processes or substantially processes, a prima facie case of either anticipation or obviousness has been established. Since the composition of the memory layer of Cheng is the same as that of the invention, the product (memory layer) of Cheng must necessarily exhibit the properties as that of the invention – the properties being that “wherein in response to the memory layer being changed from the first state to the second state or from the second state to the first state, the memory device is configured such that a ratio of Ge, As, and Se is maintained constant in the first region and the second region of the memory layer.” See MPEP 2112.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Han US PGPub. 2022/0059522 in view of Cheng et al. US Pat 10,374,009. Regarding claim 17, Han teaches a memory apparatus (fig. 13-16) [0083] comprising: a plurality of bit lines (60, fig. 13-14) [0099] extending in a first (Y, fig. 14) direction; a plurality of word lines (50, fig. 13-14) [0099] extending in a second (X, fig. 14) direction crossing the first (Y) direction; and a plurality of memory cells (MC/MC_1, fig. 13-14) [0099] at intersections between the plurality of bit lines (60) and the plurality of word lines (50), wherein the plurality of memory cells (MC) each have a memory layer (120, fig. 15-16) [0103] having Ovonic threshold switching characteristics (GeSbSeLn, [0086], [0114]) (Han, fig. 13-16). But Han fails to teach wherein the plurality of memory cells (MC) are each configured to have threshold voltages of the plurality of memory cells each be changed as a density of active traps in the plurality of memory cells is changed, the threshold voltages changing according to a polarity of and an intensity of a bias voltage applied to the plurality of memory cells, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer being changed. However, Cheng teaches a memory cell (fig. 2) (col.4, line 15) comprising a memory layer (10, fig. 2) (col.4, line 16) having Ovonic threshold switching characteristics (col.3, line 65), the plurality of memory cells (fig. 2) are configured to have threshold voltages of the plurality of memory cells each be changed as a density of active traps in the plurality of memory cells is changed, the threshold voltages changing according to a polarity of and an intensity of a bias voltage applied to the plurality of memory cells, and an element composition (AsSeGe, fig. 1-2) (col.3, lines 64-65) distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer being changed (Cheng et al., fig. 1-2, col.3, lines 3-9). The memory layer (10) of the memory cell (fig. 2) is considered to have the characteristics wherein “the memory cells are configured to have a threshold voltage of the plurality of memory cells each be changed as a density of active traps in the plurality of memory cells is changed, the threshold voltages changing according to a polarity of and an intensity of a bias voltage applied to the plurality of memory cells, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer (10) being changed” because the memory layer (10) is made of (AsSeGe, fig. 1-2) (col.3, lines 64-65) in similar composition (fig. 1, col.3, lines 3-9) as that of the invention (see GeAsSe in fig. 12, [0074] of the specification of the instant application that has the claimed characteristics [0041]). It has been held that where the claimed and the prior art products are identical or substantially identical in structure or composition (as in this case), or produced by identical processes or substantially processes, a prima facie case of either anticipation or obviousness has been established. Since the composition of the memory layer of Cheng is the same as that of the invention, the product (memory layer) of Cheng must necessarily exhibit the properties as that of the invention – the properties being that “the memory cells are configured to have a threshold voltage of the plurality of memory cells each be changed as a density of active traps in the plurality of memory cells is changed, the threshold voltages changing according to a polarity of and an intensity of a bias voltage applied to the plurality of memory cells, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer (10) being changed.” See MPEP 2112.01.
Allowable Subject Matter
Claims 4-11, 13, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a memory device wherein “in response to the memory layer being in the first state, a density of active traps in the second region is greater than a density of active traps in the first region” as recited in claim 4 in combination with the rest of the limitations of claims 1-3; a memory device wherein “in response to the memory layer being in the second state, a density of active traps in the second region is less than a density of active traps in the first region” as recited in claim 5 in combination with the rest of the limitations of claims 1-3;
a memory device wherein “a density of active traps in the first region and a density of active traps in the second region in response to the memory layer being in the second state are respectively less than the density of active traps in the first region and the density of active traps in the second region in response to the memory layer being in the first state” as recited in claim 6 in combination with the rest of the limitations of claims 1-3;
a memory device wherein “a thickness of the second region is less than a thickness of the first region” as recited in claim 7 in combination with the rest of the limitations of claims 1-3;
a memory device wherein “a total thickness of the memory layer is about 10 nm or more and about 30 nm or less, and a thickness of the second region is about 1 nm or more and about 4 nm or less” as recited in claim 8 in combination with the rest of the limitations of claims 1-3;
a memory device wherein “in response to the memory layer being in the first state, the memory layer is configured to be converted into the second state by applying a negative bias voltage to the memory layer” as recited in claim 9 in combination with the rest of the limitations of claims 1-2;
a memory device wherein “in response to the memory layer being in the second state, the memory layer is configured to be converted into the first state by applying a positive bias voltage greater than or equal to the second threshold voltage to the memory layer” as recited in claim 11 in combination with the rest of the limitations of claims 1-2;
a memory device wherein “the memory layer comprises a single layer comprising at least one material of GeAsSeIn, GeAsSeSIn, GeAsSeSbIn, GeAsSeTeIn, GeAsSeAlIn, GeSbSeIn, and GeSbSeNIn, and wherein a concentration of indium (In) in the memory layer is 10 at % or less” as recited in claim 13 in combination with the rest of the limitations of claim 1;
a memory device wherein “a difference between a concentration of Se in the first region in response to the memory layer being in the first state and the concentration of Se in the first region in response to the memory layer being in the second state is within 10% of the concentration of Se in the first region in response to the memory layer being in the first state” as recited in claim 16 in combination with the rest of the limitations of claims 1-3 and 14; and a memory apparatus wherein “each of the plurality of memory cells is configured to independently be in any one of a first state having a first threshold voltage and a second state having a second threshold voltage greater than the first threshold voltage, each of the plurality of memory cells includes a first region in contact with a corresponding bit line of the plurality of bit lines and a second region in contact with a corresponding word line of the plurality of word lines, in response to the plurality of memory cells each being in the first state, a density of active traps in the second region is greater than a density of active traps in the first region, in response to the plurality of memory cells each being in the second state, the density of active traps in the second region is less than the density of active traps in the first region, and the density of active traps in the first region and the density of active traps in the second region in response to the plurality of memory cells each being in the second state are respectively less than the density of active traps in the first region and the density of active traps in the second region in response to the plurality of memory cells each being in the first state” as recited in claim 18 in combination with the rest of the limitations of claim 17.
Claim 10 is also objected to as allowable for further limiting and depending upon allowable claim 9. Claims 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a memory apparatus wherein “the plurality of memory cell strings and the plurality of vertical bit lines are arranged to penetrate the plurality of word planes in the third direction, an area surrounded by one of the plurality of word planes in each of the plurality of memory cell strings corresponds to one memory cell” in combination with the limitation wherein “the memory cell is configured to have a threshold voltage of the memory cell be changed as a density of active traps in the memory cell is changed, the threshold voltage changed according to a polarity and an intensity of a bias voltage applied to the memory cell, and an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer being changed” as recited in claim 19.
Claim 20 is also allowed for further limiting and depending upon allowed claim 19. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Reshoko et al. US PGPub. 2023/0307352 teaches a memory device with a memory layer comprising GeAsSe (fig. 4, [0050]) but fails to specific the composition of the elements. Lee et al. US PGPub. 2022/0052116 also teaches a memory device with a memory layer comprising GeAsSeLn (fig. 5A, [0068]) but also fails to disclose the composition of the elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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