Prosecution Insights
Last updated: August 17, 2026
Application No. 18/594,454

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Mar 04, 2024
Priority
Sep 12, 2023 — JP 2023-147489
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
4100
Tech Center
4100
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
380 granted / 456 resolved
+23.3% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
20 currently pending
Career history
474
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 456 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-15 in the reply filed on 06/10/2024 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 8-9, 11-12, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyamoto et al. (US 20200161445 A1, hereinafter Miyamoto) With regards to claim 1, Miyamoto discloses a semiconductor device manufacturing method, (FIGS. 7-20) comprising: forming a mask material (hard mask HM1) having openings on a surface of a silicon carbide layer; (silicon carbide SB and EP) performing first processing for implanting at least one substance selected from a group consisting of hydrogen (H), helium (He), and electrons (Paragraph [0093]: “using the plurality of the hard mask HM1 as mask, for example, hydrogen (H) ions are implanted to form the recombination layer REC…”) into a first region of the silicon carbide layer by using the mask material as a mask; performing a first ion implantation for implanting p-type impurities into a second region shallower than the first region by using the mask material as a mask before the first processing or after the first processing; (Paragraph [0092]: “Next, aluminum ions are implanted using the plurality of the hard mask HM1 as mask to form p-type body regions BR in the epitaxial layer EP…” where the ion implanting occurs before the first processing, see FIG. 8) removing the mask material after the first processing and the first ion implantation; (See FIG. 10) and performing a first heat treatment at a temperature equal to or more than 1600°C after the removing the mask material. (See FIG. 11 and paragraph [0104]: “First, a carbon (C) film CF is formed so as to cover an upper surface of the epitaxial layer EP and a back surface of the semiconductor substrate SB. Next, for example, a heat treatment at 1700 to 1800° C….”) With regards to claim 2, Miyamoto discloses the semiconductor device manufacturing method according to claim 1, wherein the first processing includes a plurality of processes, and in each of the plurality of processes, the at least one substance is implanted up to different depths of the silicon carbide layer. (Paragraph [0093]: “The ion implantation is performed in a plurality of times…” See also FIG. 8, showing the different depths) With regards to claim 8, Miyamoto discloses the semiconductor device manufacturing method according to claim 1, wherein a depth of the first region is equal to or more than three times a depth of the second region. (see FIG. 8, where the depths of the layers REC and BR are equal in the DR direction) With regards to claim 9, Miyamoto discloses the semiconductor device manufacturing method according to claim 1, wherein a depth of the first region is equal to or more than 5 μm. (Paragraph [0138]: “setting the thickness of the recombination layer REC to 3.4 μm or more…” where the thickness can be more than 5 um) With regards to claim 11, Miyamoto discloses the semiconductor device manufacturing method according to claim 1, wherein a concentration of the at least one substance in the first region is equal to or more than 1 × 1015 cm-3 and equal to or less than 1 × 1021 cm-3. (Paragraph [0093]: ‘a total dose amount is 2×10.sup.16/cm^2…”) With regards to claim 12, Miyamoto discloses the semiconductor device manufacturing method according to claim 1 further comprising: forming a carbon film on the surface of the silicon carbide layer before the first heat treatment after the removing the mask material. (Paragraph [0104]: “First, a carbon (C) film CF is formed so as to cover an upper surface of the epitaxial layer EP…”) With regards to claim 15, Miyamoto discloses the semiconductor device manufacturing method according to claim 1, wherein the p-type impurities are aluminum (Al) or boron (B). (Paragraph [0092]: “Next, aluminum ions are implanted using the plurality of the hard mask HM1 as mask to form p-type body regions BR in the epitaxial layer EP…” where the ion implanting occurs before the first processing, see FIG. 8) Allowable Subject Matter Claims 3-7, 10, and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. SHIMIZU (US 20220302261 A1) – SiC device doped with hydrogen Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Mar 04, 2024
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707627
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
3y 8m to grant Granted Aug 11, 2026
Patent 12707702
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
3y 0m to grant Granted Aug 11, 2026
Patent 12701694
APPARATUSES INCLUDING SEMICONDUCTIVE PILLAR STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
4y 0m to grant Granted Aug 04, 2026
Patent 12701692
SEMICONDUCTOR STRUCTURE AND FORMING METHOD AND OPERATING METHOD THEREFOR
2y 8m to grant Granted Aug 04, 2026
Patent 12690283
IMAGE SENSOR
2y 9m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+9.0%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 456 resolved cases by this examiner. Grant probability derived from career allowance rate.

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