Prosecution Insights
Last updated: October 01, 2026
Application No. 18/594,551

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT

Final Rejection §101§112
Filed
Mar 04, 2024
Priority
Mar 22, 2022 — JP 2022-045799 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
2 (Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
2m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
517 granted / 827 resolved
-5.5% vs TC avg
Strong +24% interview lift
Without
With
+24.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
48 currently pending
Career history
874
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
24.7%
-15.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 827 resolved cases

Office Action

§101 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 20, 2026 was considered by the examiner. Claim Rejections - 35 USC § 112(b) Examiner withdraws the previous 35 USC § 112(b) based upon Applicant’s amendments to the claims. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 8-9, Under MPEP 2173.05(p)(II), “[a] single claim which claims both an apparatus and the method steps of using the apparatus is indefinite…”. This ruling was issued in Ex Parte Lyell, 17 USPQ2d 1548 (BPAI 1990), where the board held that a single claim cannot have both an apparatus and method of using said apparatus in it. The Federal Circuit in IPXL Holdings v. Amazon.com, Inc., 430 F.3d 1377, 1384 (Fed. Cir. 2005) adopted this holding, and further cited Robert C. Faber, Landis on Mechanics of Patent Claim Drafting § 60A (2001) with the warning to "[n]ever mix claim types to different classes of invention in a single claim.". The Court went on to hold “recit[ing] both a system and the method for using that system … does not apprise a person of ordinary skill in the art of its scope, and it is invalid under section 112, paragraph 2”.1 In the current Application claim 8 claims: 8. (Original) The semiconductor device according to claim 1, wherein: a first turn-on voltage is applied to the first electrode pad; a second turn-on voltage is applied to the second electrode pad; a third turn-on voltage is applied to the third electrode pad; a third turn-off voltage is applied to the third electrode pad, after the first turn-on voltage is applied to the first electrode pad, after the second turn-on voltage is applied to the second electrode pad, and after the third turn-on voltage is applied to the third electrode pad; a second turn-off voltage is applied to the second electrode pad after the third turn- off voltage is applied to the third electrode pad; and a first turn-off voltage is applied to the first electrode pad after the second turn-off voltage is applied to the second electrode pad. (emphasis added). Each of the above underlined limitations is a process step to use the device of claim 1. As an dependent claim, claim 8 requires all of the limitations of the independent claim 1. Therefore, the full integrated claim 8 is presented below, where claim 1 will be presented in standard font, and claim 8 will be presented italicized with the method of using steps underlined: A semiconductor device including RC-IGBT having IGBT and freewheeling diode, comprising: a transistor region including a first gate electrode provided in a first trench, a second gate electrode provided in a second trench, a third gate electrode provided in a third trench, a semiconductor layer having a first face and a second face opposed to the first face, a first semiconductor region of a first conductivity type provided in the semiconductor layer and in contact with the first face, and a second semiconductor region of a second conductivity type provided in the semiconductor layer and in contact with the first face; a diode region including a diode having a conductive layer provided in a fifth trench, and the semiconductor layer; a boundary region provided between the transistor region and the diode region, the boundary region including a fourth gate electrode provided in a fourth trench, the semiconductor layer, a third semiconductor region of the first conductivity type provided in the semiconductor layer and in contact with the first face, a fourth semiconductor region of the first conductivity type provided in the semiconductor layer and in contact with the first face, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third semiconductor region, and a fifth semiconductor region of the second conductivity type provided in the semiconductor layer and in contact with the first face; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode, wherein an occupation area ratio of the fourth semiconductor region on the first face of the boundary region is less than or equal to an occupation area ratio of the first semiconductor region on the first face of the transistor region. wherein: a first turn-on voltage is applied to the first electrode pad; a second turn-on voltage is applied to the second electrode pad; a third turn-on voltage is applied to the third electrode pad; a third turn-off voltage is applied to the third electrode pad, after the first turn-on voltage is applied to the first electrode pad, after the second turn-on voltage is applied to the second electrode pad, and after the third turn-on voltage is applied to the third electrode pad; a second turn-off voltage is applied to the second electrode pad after the third turn- off voltage is applied to the third electrode pad; and a first turn-off voltage is applied to the first electrode pad after the second turn-off voltage is applied to the second electrode pad. As one can clearly see unified claim 8 clearly contains both limitations directed to the statutory class of machines (i.e. the device), and to the statutory class of processes (i.e. method of using the device). 2 Therefore, because claim 8 is directed to two different statutory classes “it does not apprise a person of ordinary skill in the art of its scope, and it is invalid under section 112, paragraph 2”. IPXL Holdings v. Amazon.com, Inc. 430 F.3d 1377, 1384 (Fed. Cir. 2005). For the above reason claim 8 is indefinite as being indefinite under 35 USC § 112(b). Regarding claim 9, Claim 9 is rejected for the same reason as claim 8 above. Claim Rejections - 35 USC § 112(a) Examiner withdraws the 35 USC § 112(a) rejection based upon Applicant’s amendment to claim 6. Examiner notes the upper electrode is element 12 in the figures. Allowable Subject Matter Claims 1-7, and 10-16 are allowed. The following is an examiner’s statement of reasons for allowance: see below. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Regarding claim 1, the prior art does not teach: a fourth semiconductor region of the first conductivity type provided in the semiconductor layer and in contact with the first face, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third semiconductor region, and Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898 1 Access to the Federal Reporter has been removed from Examiner access. Examiner has attached the Federal Circuit’s ruling. The relevant pages are numbered pages 11-13. 2 Under 35 USC § 101 there are only four statutory classes:  processes, machines, manufactures and compositions of matter.
Read full office action

Prosecution Timeline

Mar 04, 2024
Application Filed
Apr 20, 2026
Non-Final Rejection mailed — §101, §112
Jul 20, 2026
Response Filed
Sep 18, 2026
Final Rejection mailed — §101, §112 (current)

Precedent Cases

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Patent 12751046
SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SAME
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Patent 12745427
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+24.4%)
2y 9m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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