DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable claim 1 of U.S. Patent No. 11,954,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the SoC described in claim 1 of the instant application (18/954,928) are taught in claim 1 of the patented application (U.S. Patent No. 11,954,587). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub.: 2022/0206068) in view of SONG et al. (US Pub.: 2020/0082263) and Asano (US Pub.: 2004/0041547).
As per claim 1, Kim teaches/suggests a system-on-chip (SoC) comprising a neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN), the SoC comprising: a first circuitry, disposed on a semiconductor substrate, provided for a first NPU and a second NPU ([0008]; [0016]; [0021]-[0022]; [0088]; [0101]); and a second circuitry, disposed on the semiconductor substrate, configured to operate accordingly ([0008]; [0016]; [0021]-[0022]; [0088]; [0101]), wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator (Fig. 1-3; [0150]-[0155]) (Fig. 1-3; Fig. 6; [0095]-[0101]; and [0143]-[0155])
Kim does not teach the SoC comprising:
configured to generate a control signal to selectively output one or more clock signals,
wherein the control signal to selectively output the one or more clock signals is generated based on a power measured by a power management integrated circuit,
wherein the one or more clock signals include clock signals having different phases.
SONG teaches/suggests a system comprising: configured to generate a control signal to selectively output one or more clock signals, wherein the control signal to selectively output the one or more clock signals is operating accordingly, wherein the one or more clock signals include clock signals (Fig. 1; [0026]; and [0031]-[0035]).
Asano teaches/suggests a system comprising: generated based on a power measured by a power management integrated circuit, and having different phases ([0010]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include SONG’s clock signaling architecture and Asano’s different clock phases into Kim’s system for the benefit of lowering costs and/or power consumption (SONG, [0032]) and inhibiting fluctuation of power supply voltage (Asano, [0010]) to obtain the invention as specified in claim 1.
As per claim 2, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein a first clock signal among the one or more clock signals is a first input signal of the first NPU, and wherein a second clock signal among the one or more clock signals is a second input signal of the second NPU (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 3, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein the first clock signal or the second clock signal is delayed in phase by a preset amount compared to a phase of an original clock signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 4, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC further comprising: a third circuitry, disposed on the semiconductor substrate, configured to generate the one or more clock signals including an original clock signal and one or more phase-delayed clock signals, based on the control signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 5, Kim, SONG, and Asano teach/suggest all the claimed features of claim 4 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein the third circuitry comprises: one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal; and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 6, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC further comprising: a third circuitry configured to generate one or more phase-delayed clock signals based on an original clock signal according to the control signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 7, Kim, SONG, and Asano teach/suggest all the claimed features of claim 6 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein a phase of the one or more phase-delayed clock signals is adjusted so as to reduce the measured power for the first NPU or the second NPU (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 8, Kim, SONG, and Asano teach/suggest all the claimed features of claim 6 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein based on a determination that a utilization rate of the first NPU or the second NPU is to be increased, a phase of the one or more phase-delayed clock signals is shifted or drifted compared to the phase of the original clock signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 9, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein the first clock signal has a first phase, and wherein the second clock signal has a second phase delayed from the first phase (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 10, Kim, SONG, and Asano teach/suggest all the claimed features of claim 1 above, where Kim, SONG, and Asano further teach/suggest the SoC comprising: wherein a phase of the first clock signal is identical to the phase of an original clock signal, and wherein a phase of the second clock signal is delayed from the phase of the first clock signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 11, claim 11 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
As per claim 12, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein a first clock signal among the one or more clock signals is a first input signal of the first NPU, and wherein a second clock signal among the one or more clock signals is a second input signal of the second NPU (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 13, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein the first clock signal or the second clock signal is delayed in phase by a preset amount compared to a phase of an original clock signal (Kim, Fig. 1-3; Fig. 6; [0095]-[0101]; [0143]-[0155]; SONG, Fig. 1; [0026]; [0031]-[0035]; and Asano, Fig. 2; [0010]; [0030]-[0034]), wherein it would have been obvious to one of ordinary skilled in the art that the combination of the references would further teach/suggest the above claimed features.
As per claim 14, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system further comprising: a third semiconductor chip, mounted on the substrate, configured to generate the one or more clock signals including an original clock signal and one or more phase-delayed clock signals, based on the control signal.
As per claim 15, Kim, SONG, and Asano teach/suggest all the claimed features of claim 14 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein the third semiconductor chip comprises: one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal; and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters.
As per claim 16, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system further comprising: a third semiconductor chip configured to generate one or more phase-delayed clock signals based on an original clock signal according to the control signal.
As per claim 17, Kim, SONG, and Asano teach/suggest all the claimed features of claim 16 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein a phase of the one or more phase-delayed clock signals is adjusted so as to reduce the measured power for the first NPU or the second NPU.
As per claim 18, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein based on a determination that a utilization rate of the first NPU or the second NPU is to be increased, a phase of the one or more phase-delayed clock signals is shifted or drifted compared to the phase of the original clock signal.
As per claim 19, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein the first clock signal has a first phase, and wherein the second clock signal has a second phase delayed from the first phase.
As per claim 20, Kim, SONG, and Asano teach/suggest all the claimed features of claim 11 above, where Kim, SONG, and Asano further teach/suggest the system comprising: wherein a phase of the first clock signal is identical to the phase of the original clock signal, and wherein a phase of the second clock signal is delayed from the phase of the first clock signal.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 August 29, 2026
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