DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20230061475 A1 to Yun (hereinafter “Yun”).
Regarding claim 1, Yun teaches a semiconductor device (fig. 10 with figs. 9A-9C used as references to clearly indicate the necessary elements present in fig. 10), comprising:
a selector pattern (113; fig. 9C) [0020] including an insulating material (doped chalcogenide; selenium; a chalcogenide being an insulative material) [0042] having dopants (elements in the material which affect the host elements electrical behavior, present in “doped chalcogenide”; see ¶ [0042]) implanted (product-by-process limitation, non-limiting to a device) to the insulating material (material of 113) along an implantation direction (vertical direction, see below) and having a first sidewall (left side in the x direction; fig. 9B) and a second sidewall (right side in the x direction; fig. 9B) facing the first sidewall (left), the selector pattern (113) configured to exhibit different electrical conducting characteristics (see ¶ [0041]-[0042] wherein the selector functions as a filament selector) in response to an applied voltage (as part of the selector material) [0041] with respect to a threshold voltage (as part of the selector material) [0041]; and
a first electrode layer (114E on left side of 113; fig. 9B) [0025] and a second electrode layer (114E on right side of 113; fig. 9B) [0025] respectively formed over the first sidewall (left) and the second sidewall (right) of the selector pattern (113),
wherein the implantation direction (vertical) of the dopants (elements added to chalcogenide) is different from a direction (horizontal) of a current flowing (current which effects the threshold voltage) through the selector pattern (113) between the first electrode layer (left 114E) and the second electrode layer (right 114E) when the selector pattern (113) is turned on (when the value exceeds threshold of selector material) [0041]-[0042].
Regarding the implantation direction, the term does not structurally distinguish or structurally limit the arrangement of the dopants in the layer. Yun teaches dopants and has current flow during operation. The recitation comparing the implantation direction to the direction of current flow does not distinguish over the reference in a claim to the device itself. Indeed, the recitation of implantation of dopants and implantation direction are considered as product by process limitations. Thus, the claim is not limited by the manipulation of recited steps but only by the resulting structure. M.P.E.P. 2113 I. In the interest of compact prosecution, when the term “implantation direction” is used in the claim, a vertical direction is used. Furthermore, the term “implanted” is not limiting, but the implied presence of dopants in the device does limit the structure and is considered in the context of the rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3-4, 7-8, 10-11, 13-15, 17-19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yun, as applied to claim 1 above, and in view of U.S. Pat. Pub. No. US 20230142183 A1 to Dong et al. (hereinafter “Dong”).
Regarding claim 3, Yun teaches the semiconductor device according to claim 1, further comprising: a first contact plug (line 84; fig. 10) [0076] having an upper surface (vertically upper) in contact (electrically) with a lower surface (vertically lower) of the first electrode layer (left 114E) and disposed under (vertically) the first electrode layer (left 114E); and a second contact plug (line 224; fig. 10) [0076].
Yun does not teach the second contact plug having a sidewall in contact with the second electrode layer at one side of the second electrode layer.
Dong, however, teaches semiconductor device (memory structure of fig. 8F) comprising an ovonic switching material (123; fig. 8F) wherein the structure comprises a second contact plug (second line 250; fig. 8F) [0141] having a sidewall (lateral side) in contact (electrically) with the second electrode layer (electrode 229; fig. 8F) [0130].
It would have been obvious to a person of ordinary skill in the art to modify the structure of Yun to comprise a plug meeting the limitations of claim 10 to allow for a front side and back-side contact, allowing for an increase in circuit density i.e., decreasing footprint as shown by Dong in fig. 8F.
Regarding claim 4, Yun in view of Dong teaches the semiconductor device according to claim 3, further comprising: a first conductive line (lines in layer M1; fig. 10) [0076] connected to the first contact plug (84) and disposed under the first contact plug (84); and a second conductive line (lines in layer M7; fig. 10) [0076] connected to the second contact plug (224) and disposed over the second contact plug (224).
Regarding claim 7, Yun teaches the semiconductor device according to claim 1, further comprising: a memory pattern (memory array TM; fig. 9B) [0060] having an upper surface in contact (electrically; see fig. 9B) with a lower surface (vertically lower) of the first electrode layer (left 11E) and disposed under (vertically) the first electrode layer (left 114E);
Yun does not teach a second contact plug having a sidewall in contact with the second electrode layer at one side of the second electrode layer.
Dong, however, teaches semiconductor device (memory structure of fig. 8F) comprising an ovonic switching material (123; fig. 8F) wherein the structure comprises a second contact plug (second line 250; fig. 8F) [0141] having a sidewall (lateral side) in contact (electrically) with the second electrode layer (electrode 229; fig. 8F) [0130].
It would have been obvious to a person of ordinary skill in the art to modify the structure of Yun to comprise a plug meeting the limitations of claim 10 to allow for a front side and back-side contact, allowing for an increase in circuit density i.e., decreasing footprint as shown by Dong in fig. 8F.
Regarding claim 8, Yun in view of Dong teaches the semiconductor device according to claim 7, further comprising: a first conductive line (84) connected to the memory pattern (TM) and disposed under the memory pattern (TM); and a second conductive line (M7) connected to the second contact plug (224) and disposed over the second contact plug (224).
Regarding claim 10, Yun teaches a semiconductor device (fig. 10 with figs. 9A-9C used as references to clearly indicate the necessary elements present in fig. 10) comprising:
a first conductive line (lines in layer M1; fig. 10) [0076] and a second conductive line (lines in layer M7; fig. 10) [0076] that are spaced apart (separated) from each other in a vertical direction (z direction; fig. 10);
a selector pattern (113 present in TN; fig. 9C) [0020] interposed (disposed therebetween) between the first conductive line (M1) and the second conductive line (M7) in the vertical direction (z) and including a first sidewall (left side in the x direction; fig. 9B) and a second sidewall (right side in the x direction; fig. 9B) facing the first sidewall (left) in a horizontal direction (x direction), the selector pattern (113) configured to exhibit different electrical conducting characteristics (see ¶ [0041]-[0042] wherein the selector functions based on a threshold voltage) in response to an applied voltage (as part of the selector material) with respect to a threshold voltage (as part of the selector material);
a first electrode layer (114E on left side of 113; fig. 9B) [0025] and a second electrode layer (114E on right side of 113; fig. 9B) [0025] respectively formed over the first sidewall (left) and the second sidewall (right) of the selector pattern (113);
a first contact plug (line 84; fig. 10) [0076] having an upper surface (vertically upper) in contact (electrically from below) with a lower surface (vertically lower) of the first electrode layer (left 114E), the first contact plug (84) electrically connected to the first conductive line (M1) and disposed over the first conductive line (M1); and
a second contact plug (line 224) disposed at one side (horizontally shifted) of the second electrode layer (right 114E) in the horizontal direction (x direction), the second contact plug (224) electrically connected to the second conductive line (M7) and disposed under the second conductive line (M7).
Yun does not teach:
the second contact plug having a sidewall in contact with the second electrode layer.
Dong, however, teaches semiconductor device (memory structure of fig. 8F) comprising an ovonic switching material (123; fig. 8F) wherein the structure comprises a second contact plug (second line 250; fig. 8F) [0141] having a sidewall (lateral side) in contact (electrically) with the second electrode layer (electrode 229; fig. 8F) [0130].
It would have been obvious to a person of ordinary skill in the art to modify the structure of Yun to comprise a plug meeting the limitations of claim 10 to allow for a front side and back-side contact, allowing for an increase in circuit density i.e., decreasing footprint as shown by Dong in fig. 8F.
Regarding claim 11, Yun in view of Dong teaches the semiconductor device according to claim 10, wherein the selector pattern (113) includes an insulating material (doped chalcogenide; selenium, a chalcogenide being an insulative material) [0042] implanted (product-by-process limitation, non-limiting to a device) to the insulating material (material of 113) along an implantation direction (vertical, see below) that is different from a direction (horizontal) of a current flowing (current which effects the threshold voltage) through the selector pattern (113) between the first electrode layer (left 114E) and the second electrode layer (right 114E) in response to the selector pattern (113) being turned on (when value exceeds threshold of selector material) [0041]-[0042].
Regarding the implantation direction, the term does not structurally distinguish or structurally limit the arrangement of the dopants in the layer. Yun teaches dopants and has current flow during operation. The recitation comparing the implantation direction to the direction of current flow does not distinguish over the reference in a claim to the device itself. Indeed, the recitation of implantation of dopants and implantation direction are considered as product by process limitations. Thus, the claim is not limited by the manipulation of recited steps but only by the resulting structure. M.P.E.P. 2113 I. In the interest of compact prosecution, when the term “implantation direction” is used in the claim, although it does not limit the claim, a vertical direction is used. Furthermore, the term “implanted” is not limiting, but the implied presence of dopants in the device does limit the structure and is considered in the context of the rejection.
Regarding claim 13, Yun in view of Dong teaches the semiconductor device according to claim 10, wherein the selector pattern (113) includes a first selector pattern (overlying exponential type selector material; fig. 9B) [0042] and a second selector pattern (underlying threshold type selector; fig. 9B) [0042] that are arranged in the horizontal direction (present at least in the horizontal direction on the sidewalls of the elements 114E; fig. 9B), the first electrode layer (left 114E) includes a first portion (vertically upper portion) and a second portion (vertically lower portion) that are respectively formed over first sidewalls (left sidewall of fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the second electrode layer (right 114E) includes a first portion (vertically upper) and a second portion (vertically lower) that are respectively formed over second sidewalls (right sidewall of fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the first contact plug (84) includes a first portion (upper portion) contacting (electrically) the first portion (upper) of the first electrode layer (left 114E) and a second portion (lower) contacting (electrically) the second portion (lower) of the first electrode layer (left 114E), and the second contact plug (224) includes a first portion (upper portion) contacting (electrically) the first portion (upper) of the second electrode layer (right 114E) and a second portion (lower portion i.e., of the plug 224) contacting (electrically) the second portion (lower) of the second electrode layer (right 114E).
Regarding claim 14 Yun in view of Dong teaches the semiconductor device according to claim 13, wherein the first portion (upper) of the second electrode layer (right 114E) and the second portion (lower) of the first electrode layer (left 114E) are disposed to face each other (be separated horizontally).
Regarding claim 15, Yun in view of Dong teaches the semiconductor device according to claim 10, wherein the selector pattern (113) includes a first selector pattern (overlying exponential type selector material; fig. 9B) [0042] and a second selector pattern (underlying threshold type selector; fig. 9B) [0042] that are arranged in the horizontal direction (present at least in the horizontal direction on the sidewalls of the elements 114E; fig. 9B), the first electrode layer (first 114E) includes a first portion (vertically upper) and a second portion (vertically lower) that are respectively formed over first sidewalls (left sidewall in fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the second electrode layer (right 114E) includes a first portion (upper portion) and a second portion (lower portion) that are respectively formed over second sidewalls (right sidewall) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the first contact plug (84) includes a first portion (upper portion) contacting (electrically) the first portion (upper) of the first electrode layer (left 114E) and a second portion (lower portion i.e., of plug 84) contacting (electrically) the second portion (lower) of the first electrode layer (left 114E), and the first portion (upper) and the second portion (lower) of the second electrode layer (right 114E) face each other (on other horizontal sides) and are in common contact (common electrical contact) with the second contact plug (224).
Regarding claim 17, Yun in view of Dong teaches the semiconductor device according to claim 10, further comprising: a memory pattern interposed between the second contact plug and the second conductive line.
Regarding claim 18, Yun teaches a semiconductor device (fig. 10 with figs. 9A-9C used as references to clearly indicate the necessary elements present in fig. 10), comprising:
a first conductive line (lines in layer M1; fig. 10) [0076] and a second conductive line (lines in layer M7; fig. 10) [0076] that are spaced apart (separated) from each other in a vertical direction (z direction; fig. 10);
a selector pattern (113 present in TN; fig. 9C) [0020] interposed (disposed therebetween) between the first conductive line (M1) and the second conductive line (M7) in the vertical direction (z) and including a first sidewall (left side in the x direction; fig. 9B) and a second sidewall (right side in the x direction; fig. 9B) that face each other in a horizontal direction (x direction);
a first electrode layer (114E on left side of 113; fig. 9B) [0025] and a second electrode layer (114E on right side of 113; fig. 9B) [0025] respectively formed over the first sidewall (left) and the second sidewall (right) of the selector pattern (113);
a memory pattern (memory array TM; fig. 9B) [0060] having an upper surface (vertically upper) in contact with a lower surface (vertically lower) of the first electrode layer (left 114E), the memory pattern (TM) electrically connected to the first conductive line (M1) and disposed over the first conductive line (M1); and
a contact plug (line 224) disposed at one side (horizontally shifted) of the second electrode layer (right 114E) in the horizontal direction (x), the contact plug (224) electrically connected to the second conductive line (M7) and disposed under (vertically under) the second conductive line (M7).
Yun does not teach:
the contact plug having a sidewall in contact with the second electrode layer.
Dong, however, teaches semiconductor device (memory structure of fig. 8F) comprising an ovonic switching material (123; fig. 8F) wherein the structure comprises a second contact plug (second line 250; fig. 8F) [0141] having a sidewall (lateral side) in contact (electrically) with the second electrode layer (electrode 229; fig. 8F) [0130].
It would have been obvious to a person of ordinary skill in the art to modify the structure of Yun to comprise a plug meeting the limitations of claim 10 to allow for a front side and back-side contact, allowing for an increase in circuit density i.e., decreasing footprint as shown by Dong in fig. 8F.
Regarding claim 19, Yun in view of Dong teaches the semiconductor device according to claim 18, wherein the selector pattern (113) includes an insulating material (doped chalcogenide; selenium, a chalcogenide being an insulative material) [0042] having dopants (elements in the material which affect the host elements electrical behavior, present in “doped chalcogenide”; see ¶ [0042]) implanted (product-by-process limitation, non-limiting to a device) to the insulating material (material of 113) along an implantation direction (vertical, see below) that is different from a direction (horizontal of a current flowing (current which effects the threshold voltage) through the selector pattern (113) between the first electrode layer (left 114E) and the second electrode layer (right 114E) in response to the selector pattern (113) being turned on (when value exceeds threshold of selector material) [0041]-[0042].
Regarding the implantation direction, the term does not structurally distinguish or structurally limit the arrangement of the dopants in the layer. Yun teaches dopants and has current flow during operation. The recitation comparing the implantation direction to the direction of current flow does not distinguish over the reference in a claim to the device itself. Indeed, the recitation of implantation of dopants and implantation direction are considered as product by process limitations. Thus, the claim is not limited by the manipulation of recited steps but only by the resulting structure. M.P.E.P. 2113 I. In the interest of compact prosecution, when the term “implantation direction” is used in the claim, although it does not limit the claim, a vertical direction is used. Furthermore, the term “implanted” is not limiting, but the implied presence of dopants in the device does limit the structure and is considered in the context of the rejection.
Regarding claim 21, Yun in view of Dong teaches the semiconductor device according to claim 18, wherein the selector pattern (113) includes a first selector pattern (overlying exponential type selector material; fig. 9B) [0042] and a second selector pattern (underlying threshold type selector; fig. 9B) [0042] that are arranged in the horizontal direction (present at least in the horizontal direction on the sidewalls of the elements 114E; fig. 9B), the first electrode layer (left 114E) includes a first portion (vertically upper portion) and a second portion (vertically lower portion) that are respectively formed over first sidewalls (left sidewall of fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the second electrode layer (right 114E) includes a first portion (vertically upper) and a second portion (vertically lower) that are respectively formed over second sidewalls (right sidewall of fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), and the contact plug (250) includes a first portion contacting (electrically) the first portion (upper) of the second electrode layer (right 114E) and a second portion (lower) contacting (electrically) the second portion (lower) of the second electrode layer (right 114E).
Regarding claim 22, Yun in view of Dong teaches the semiconductor device according to claim 21, wherein the first portion (upper) of the second electrode layer (right 114E) and the second portion (lower) of the first electrode layer (left 114E) face each other (are separated horizontally).
Regarding claim 23, Yun in view of Dong teaches the semiconductor device according to claim 18, wherein the selector pattern (113) includes a first selector pattern (overlying exponential type selector material; fig. 9B) [0042] and a second selector pattern (underlying threshold type selector; fig. 9B) [0042] that are arranged in the horizontal direction (present at least in the horizontal direction on the sidewalls of the elements 114E; fig. 9B), the first electrode layer (first 114E) includes a first portion (vertically upper) and a second portion (vertically lower) that are respectively formed over first sidewalls (left sidewall in fig. 9B) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), the second electrode layer (right 114E) includes a first portion (upper portion) and a second portion (lower portion) that are respectively formed over second sidewalls (right sidewall) of the first selector pattern (overlying exponential 113) and the second selector pattern (underlying threshold 113), and the first portion (upper) and the second portion (lower) of the second electrode layer (right 114E) face each other (on other horizontal sides) and are in common contact (common electrical contact) with the second contact plug (224).
Allowable Subject Matter
Claims 2, 5-6, 9, 12, 16, & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, it is not found a reference which would reasonably read on the limitations of claim 2. In specific, most of the references found, including, Yun, teach electrodes which become less wide at their vertically lowermost portion, the opposite of what is required in claim 2. Claims 12 and 20 comprise allowable subject matter for the same reason as claim 2.
Regarding claim 5, it is not found a reference which would reasonably read on the limitations of claim 5. The closest reference found is US 20220285611 A1 to Hsu et al. which teaches a memory pattern between a contact plug and a conductive line (see fig. 7, elements MS1, 115w+1, and 115w), but the conductive line is not connected to an electrode, as required by claim 5 (i.e., as required by a claim which claim 5 depends on). Claim 16 is allowable for similar reasons.
Regarding claim 6, it is not found a reference which would reasonably read on the limitations of claim 6. The closest reference found is US 20220285611 A1 to Hsu et al. which teaches a memory pattern between a contact plug and a conductive line (see fig. 7, elements MS1, 115w+1, and 115w), but the contact plug does not have a sidewall in contact with an electrode, as required by claim 6 (i.e., as required by a claim which claim 6 depends on).
Regarding claim 9, it is not found a reference which would reasonably read on the limitations of claim 9. Indeed, for similar reasons as claim 2, most memory pattern have a width that increase in a downward direction, this width relationship being related to the width of the electrodes, as these elements are often defined by one another in the references found. Yun is the closest reference regarding this subject matter.
Conclusion
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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