Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-7 rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. Patent Pub. No. 2011/0101453) of record, in view of Park (KR 960015323) of record.
Regarding Claim 1
FIG. 1H of Lin discloses a device, comprising: an epitaxial layer (102) of a first conductivity type (p) over a substrate (100); a plurality of wells (210/214/218) of a second conductivity type (n) in the epitaxial layer; a first slot region (212) of the first conductivity type in the epitaxial layer, the first slot region interposing a first one and a second one of the plurality of wells of the second conductivity type; a well (216) of the first conductivity type forming an interface with a third one (214) of the plurality of wells of the second conductivity type; a gate structure (226) over the interface of the well of the first conductivity type and the third one of the plurality of wells of the second conductivity type; (FIG. 1D) a first source/drain region (118) in the well of the first conductivity type (112); and a second source/drain region (116) in the first one and the second one of the plurality of wells of the second conductivity type (110), and over the first slot region of the first conductivity type, wherein the first slot region of the first conductivity type forms a p-n junction with the first one of the plurality of wells of the second conductivity type.
Lin is silent with respect to “the p-n junction meets the second source/drain region at a bottom surface of the second source/drain region”.
FIG. 7 of Park discloses a similar device, wherein the first slot region (503) of the first conductivity type forms a p-n junction with the first one (505) of the plurality of wells of the second conductivity type, wherein the p-n junction meets the second source/drain region (506) at a bottom surface of the second source/drain region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lin, as taught by Park. The ordinary artisan would have been motivated to modify Lin in the above manner for purpose of high voltage and current (text of Park).
Regarding Claim 4
FIG. 1H of Lin discloses the first slot region (212) of the first conductivity type has a height less than a height of the well of the first conductivity type (216).
Regarding Claim 5
FIG. 7 of Park discloses a second slot region of the first conductivity type in the epitaxial layer and interposing the second one and the third one of the plurality of wells of the second conductivity type.
Regarding Claim 6
FIG. 7 of Park discloses the second slot region of the first conductivity type has a top surface higher than a top surface of the first slot region.
Regarding Claim 7
FIG. 7 of Park discloses the gate structure overlaps with the second slot region of the first conductivity type.
Claims 2 and 3 rejected under 35 U.S.C. 103 as being unpatentable over Lin and Park, in view of Yashita (U.S. Patent Pub. No. 2004/0155257) of record.
Regarding Claim 2
Lin as modified by Park discloses Claim 1.
Lin as modified by Park is silent with respect to “the first slot region of the first conductivity type has a bottom surface interfacing the substrate”.
FIG. 2 of Yashita discloses a similar device, wherein the first slot region of the first conductivity type (54) has a bottom surface interfacing the substrate (50).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lin, as taught by Yashita. The ordinary artisan would have been motivated to modify Lin in the above manner for purpose of avoiding undesired substrate current injection ([0005] of Yashita).
Regarding Claim 3
FIG. 2 of Yashita discloses the first slot region of the first conductivity type has a top surface interfacing the second source/drain region.
Claims 8-10 rejected under 35 U.S.C. 103 as being unpatentable over Lin and Park, in view of Yeh (U.S. Patent Pub. No. 2017/0271511) of record.
Regarding Claim 8
Lin as modified by Park discloses Claim 5.
Lin as modified by Park is silent with respect to “a reduced surface field (RESURF) oxide layer extending from below the gate structure to the second source/drain region, wherein the RESURF oxide layer is over the second slot region of the first conductivity type”.
FIG. 4 of Yeh discloses a similar device, comprising a reduced surface field (RESURF) oxide layer (46) extending from below the gate structure (24) to the second source/drain region (20), wherein the RESURF oxide layer is over the second slot (40) region of the first conductivity type.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lin, as taught by Yeh. The ordinary artisan would have been motivated to modify Lin in the above manner for purpose of high voltage/current ([0003] of Yeh).
Regarding Claim 9
FIG. 4 of Yeh discloses the RESURF oxide layer (46) non-overlaps with the first slot region of the first conductivity type.
Regarding Claim 10
FIG. 4 of Yeh discloses the gate structure comprises a gate dielectric layer (22) and a gate electrode (24) over the gate dielectric layer, and the RESURF oxide layer (46) has a thickness greater than a thickness of the gate dielectric layer.
Claims 11-16 rejected under 35 U.S.C. 103 as being unpatentable over Schneider (U.S. Patent Pub. No. 2003/0011021) of record, in view of Chiang (U.S. Patent Pub. No. 2015/0091085) of record, in view of Yeh.
Regarding Claim 11
FIG. 2 (annotated below) of Schneider discloses a device, comprising: a p-type epitaxial layer (up portion of 7 forming p/n wells) over a substrate (7); a plurality of n-type wells (11) in the p-type epitaxial layer, each of the plurality of n-type wells having a bottom surface entirely in contact with the substrate; a p-type well (9) interfacing a first one of the plurality of n-type wells; a first n-type buried layer (8) in the substrate, the p-type well overlapping with the first n-type buried layer.
PNG
media_image1.png
306
474
media_image1.png
Greyscale
Schneider is silent with respect to “a source region in the p-type well; a drain region in a second one of the plurality of n-type wells; and a gate structure laterally between the source region and the drain region” and “the first n-type buried layer has a width less than a width of the p-type well when measured in a direction parallel with a top surface of the substrate”.
FIG. 13 of Chiang discloses a similar device, comprising a source region (224) in the p-type well (220); a drain region (224) in a second one (210) of the plurality of n-type wells, wherein the p-type well (220) overlapping with an entirety of the first n-type buried layer (216, one of ordinary skill in the art would understand 210 and 216 can be n type and 220 can be p type).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Chiang. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of avoiding undesired substrate current injection ([0005] of Chiang).
Schneider as modified by Chiang is silent with respect to “the first n-type buried layer has a width less than a width of the p-type well when measured in a direction parallel with a top surface of the substrate”.
FIG. 1 of Yeh discloses a similar device, wherein the first n-type buried layer (42, one of ordinary skill in the art would understand 42 can be n type and 38 can be p type) has a width less than a width of the p-type well (38) when measured in a direction parallel with a top surface of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Yeh. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of high voltage/current ([0003] of Yeh).
Regarding Claim 12
FIG. 2 (annotated above) of Schneider discloses the first n-type buried layer has opposite sidewall boundaries laterally set back from opposite sidewall boundaries of the p-type well, respectively.
Regarding Claim 13
FIG. 2 (annotated above) of Schneider discloses the first n-type buried layer overlaps with none of the plurality of n-type wells.
Regarding Claim 14
FIG. 13 of Chiang discloses a first p-type slot region (210) directly below the gate structure, the first p-type slot region spacing apart the first one of the n-type wells from the second one of the n-type wells.
Regarding Claim 15
FIG. 4 of Yeh discloses a second p-type slot region (40A) directly below the drain region (126), the second p-type slot region spacing apart the second one of the n-type wells from a third one of the n-type wells.
Regarding Claim 16
FIG. 13 of Chiang discloses the first p-type slot region (left 210) has a top surface higher than a top surface of the second p-type slot region (right 210).
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Schneider, Chiang and Yeh, in view of Mellin (EP 1271659) of record
Regarding Claim 17
Schneider as modified by Chiang and Yeh discloses Claim 11.
Schneider as modified by Chiang and Yeh is silent with respect to “a second n-type buried layer cupping an underside of the first n-type buried layer, the second n-type buried layer has an n-type impurity concentration lower than an n-type impurity concentration of the first n-type buried layer”.
FIG. 2 of Mellin discloses a similar device, comprising a second n-type buried layer (3) cupping an underside of the first n-type buried layer (4), the second n-type buried layer has an n-type impurity concentration lower than an n-type impurity concentration of the first n-type buried layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Mellin. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of increasing the parasitic PNP triggering voltage (text of Mellin).
Claims 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Schneider, in view of Chiang, in view of Salcedo (U.S. Patent Pub. No. 2014/0339601) of record, in view of Yeh.
Regarding Claim 18
FIG. 2 (annotated above) of Schneider discloses a method, comprising: forming an n-type buried layer (8) in a substrate (7); forming a p-type well (9) over the n-type buried layer, the p-type well having a bottom surface extending past opposite sidewall boundaries of the n-type buried layer; forming a plurality of n-type wells (11) in the p-type epitaxial layer, wherein the plurality of n-type wells are alternately arranged a plurality of slot regions within the p-type epitaxial layer.
Schneider is silent with respect to “epitaxially growing a p-type epitaxial layer over the substrate and the n-type buried layer”; “the n-type buried layer has a width less than a width of the p-type well when measured in a direction parallel with a top surface of the substrate”; and “forming a gate structure extending across an interface between the p-type well and a first one of the n-type wells; forming a source region in the p-type well; and forming a drain region over a first one of the slot regions”.
FIG. 13 of Chiang discloses a similar method, comprising forming a gate structure (240) extending across an interface between the p-type well and a first one of the n-type wells; forming a source region (224) in the p-type well; and forming a drain region (224) over a first one of the slot regions.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Chiang. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of avoiding undesired substrate current injection ([0005] of Chiang).
Schneider as modified by Chiang is silent with respect to “epitaxially growing a p-type epitaxial layer over the substrate and the n-type buried layer” and “the n-type buried layer has a width less than a width of the p-type well when measured in a direction parallel with a top surface of the substrate”.
FIG. 3 of Salcedo discloses a similar method, comprising epitaxially growing a p-type epitaxial layer (91) over the substrate (81) and the n-type buried layer (89).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Salcedo. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of improving protection ([0029] of Salcedo).
Schneider as modified by Chiang and Salcedo is silent with respect to “the n-type buried layer has a width less than a width of the p-type well when measured in a direction parallel with a top surface of the substrate”.
FIG. 1 of Yeh discloses a similar device, wherein the first n-type buried layer (42, one of ordinary skill in the art would understand 42 can be n type and 38 can be p type) has a width less than a width of the p-type well (38) when measured in a direction parallel with a top surface of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Schneider, as taught by Yeh. The ordinary artisan would have been motivated to modify Schneider in the above manner for purpose of high voltage/current ([0003] of Yeh).
Regarding Claim 19
FIG. 13 of Chiang discloses the gate structure (240) is formed over a second one of the slot regions.
Regarding Claim 20
FIG. 2 (annotated above) of Schneider discloses each of the plurality of n-type wells has a bottom surface entirely in contact with the substrate.
Pertinent Art
US 20140070315, 20170272093, 20210118987, 20170358570, 20080290410; CN 211555896, 104620388, 114093866; JP 2006210861, H03205832, H0444261; KR 20010037586.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 11 and 18 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Prosecution Insights