DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 1, Modifications A1, B1, and C1 in the reply filed on 23 June 2026 is acknowledged. Claims 1-20 are pending in the application, with claims 12-20 withdrawn from consideration. Applicant submits claims 1-11 read on the elected species/modifications. Claim 5 is drawn to non-elected modification A2 (Fig. 18). However, this claim is being considered in the present application, therefore the restriction requirement of 04/28/2026 is partially withdrawn. Specifically, the election requirement between modifications A1 and A2, only, is withdrawn. Claims 1-11 are treated on the merits in this Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam Jae Lee et al. (US 20220149053 A1; hereinafter Lee).
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Regarding Claim 1, Lee discloses a semiconductor device (Fig. 4, Fig. 5, Annotated Fig. 5) comprising:
a stacked film (90; ¶0055) including a plurality of electrode layers (49; ¶0065) and a plurality of first insulators (41; ¶0065) alternately in a first direction (up/down), a top layer (top of 41; hereinafter T41) of the stacked film being a second insulator that is one of the plurality of first insulators (41);
a columnar portion (60/61) including a third insulator (63; ¶0056) provided on a side face of the stacked film, a charge storage layer (65; ¶0056) provided on a side face of the third insulator (63), a fourth insulator (67; ¶0056) provided on a side face of the charge storage layer (65), and a first semiconductor layer (CL; ¶0069) provided on a side face of the fourth insulator (67), the columnar portion (60/61) being provided in the stacked film (90),
a metal layer (70; ¶0072, ¶0076) provided on the stacked film (90) and the columnar portion (60/61), electrically connected to the first semiconductor layer (CL) (Fig. 5; ¶0068-¶0078), and including one or more layers (71/73),
wherein an upper end of the columnar portion (Annotated Lee Fig. 5; UECP) is provided at a height between an upper face (top of T41) and a lower face (bottom of T41) of the second insulator (T41), and
a lower end (Annotated Fig. 5; L73) of a highest layer (73) among the one or more layers (71/73) is provided at a position lower than the upper face of the second insulator (top of T41) (as shown in annotated Fig. 5).
Regarding Claim 2, Lee discloses the device of claim 1, wherein the lower end of the highest layer (L73) is provided at a position higher than the lower face of the second insulator (bottom of T41) (as shown in Annotated Fig. 5).
Regarding Claim 3, Lee discloses the device of claim 1, wherein the highest layer (73) is an interconnect material layer in an interconnect layer that includes the metal layer (73 is an interconnect material layer commensurate in scope with the definition of “interconnect material layer” provided in the instant specification at ¶0048; wherein “The interconnect material layer of the present embodiment is a main layer in the interconnect layer and occupies a maximum volume in the interconnect layer”).
Regarding Claim 4, Lee discloses the device of claim 3, wherein the one or more layers further include a barrier metal layer (71; ¶0072) provided below the interconnect material layer (73).
Regarding Claim 5, Lee discloses the device of claim 1, further comprising a second semiconductor layer (DS; ¶0069) provided between the first semiconductor layer (CL) and the metal layer (70).
Regarding Claim 6, Lee discloses the device of claim 1, wherein an upper face of the columnar portion (UECP) is tilted relative to a plane orthogonal to the first direction (up/down) (as shown in Annotated Fig. 5).
Regarding Claim 8, Lee discloses the device of claim 1, wherein the columnar portion further includes a fifth insulator (CO; ¶0069) provided on a side face of the first semiconductor layer (CL).
Regarding Claim 9, Lee discloses the device of claim 8, wherein an upper end of the first semiconductor layer (top of CL at location indicated by the arrow of UECP in Annotated Fig. 5) is provided at a position higher than a triple point (annotated Fig. 5; TP) where the first semiconductor layer (CL), the fifth insulator (CO) and the metal layer (70) contact one another (TP is where 70 and CL are in electrical contact, and where CL and CO are in physical contact).
Regarding Claim 10, Lee discloses the device of claim 9, wherein a thickness of the first semiconductor layer (CL) at a position higher than the triple point (TP) is smaller than a thickness of the first semiconductor layer (CL) at a position lower than the triple point (TP) (as shown in Annotated Fig. 5; wherein the top of CL decreases in thickness upward from TP).
Regarding Claim 11, Lee discloses the device of claim 10, wherein the thickness of the first semiconductor layer (CL) at a position higher than the triple point (TP) decreases with a height from the triple point (as shown in Annotated Fig. 5; wherein the top of CL decreases in thickness upward from TP).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding Claim 7, Lee discloses the device of claim 1. Lee is silent regarding explicitly disclosing wherein the metal layer (70) is included in a source line, and a highest electrode layer among the plurality of electrode layers (49) is included in a source-side select line.
However, Lee teaches configuring the memory device multiple ways is a result effective variable of the desired orientation of the device (Fig. 2A and Fig. 2B; ¶0037-¶0053), configuring the top line (49) as a source select line or drain select line (¶0041-¶0052).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to configure the device of Lee with the metal layer included in a source line and the highest electrode as a source select line in order to provide a device with the desired orientation.
Furthermore, Applicant has not presented persuasive evidence that the claimed orientation/configuration is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed orientation/configuration). Also, the applicant has not shown that the claimed orientation/configuration produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art., it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to orient/configure the device of Lee by re-arranging the orientation/configuration of the source/drain lines and source/drain select lines with a reasonable expectation of success since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see MPEP 2144.04 VI.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jaeduk Lee et al. (US 20250014644 A1) discloses in Fig. 27B a similar configuration for the features of Claim 1, including a metal layer (49) with a lower surface at a level between the upper/lower faces of a top insulator layer (23) of a stacked film (23/29), wherein a columnar portion includes the claimed insulators and semiconductor channel layer.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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