Prosecution Insights
Last updated: April 19, 2026
Application No. 18/595,159

TESTER WITH SELF-TEST FUNCTIONS

Non-Final OA §102§103
Filed
Mar 04, 2024
Examiner
ALLGOOD, ALESA M
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fluke Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
527 granted / 641 resolved
+14.2% vs TC avg
Strong +18% interview lift
Without
With
+18.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
19 currently pending
Career history
660
Total Applications
across all art units

Statute-Specific Performance

§101
3.7%
-36.3% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 641 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement 2. The information disclosure statement (IDS) submitted on 9/6/2024 is considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 14, 15, 17, 20 is is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Mitchell (US 4804908) hereinafter ‘Mitchell’. Regarding Claim 14, Mitchell discloses a method of conducting self-tests on a tester (Abstract, Clm 1 A battery operated digital test instrument for measuring AC voltage, for measuring DC voltage and for performing self-test in three different modes), comprising: receiving a user input (Abstract A digital voltage and continuity test instrument for use by electricians; Abstract the display provides a reading proportionate to the battery voltage level of the instrument, Fig. 1, display 12 and Fig. 1 switch 16 for selections between various modes); controlling, based on the user input, one or more switches to couple a signal source in the tester to a to-be-tested component of a measurement circuit of the tester(Abstract he display provides a reading proportionate to the battery voltage level of the instrument, Fig. 1, display 12 and Fig. 1 switch 16 for selections between various modes); and conducting a self-test based on an electrical property at a node adjacent to the to-be-tested component (Abstract, Clm 1). Regarding Claim 15, Mitchell further discloses wherein receiving the user input comprises receiving the user input through a user selection mechanism on a user interface of the tester (Abstract A digital voltage and continuity test instrument for use by electricians; Abstract the display provides a reading proportionate to the battery voltage level of the instrument, Fig. 1, user interface as display 12 and Fig. 1 switch 16 for selections by user between various modes). Regarding Claim 17, Mitchell further discloses detecting the electrical property at the node adjacent to the to-be-tested component; and determining a result of the self-test based on the electrical property (Col. 3, Line 50-Col. 4, Line 9 use of leads to establish test voltage in circuit). Regarding Claim 20, Mitchell further discloses presenting a qualitative component of a result of the self-test through a user interface of the tester (Col. 4, Lines 36-42 Battery terminal 142 is connected to battery 140 to energize the electronic integrated circuits whereby lead continuity may be verified. With the lead open the LCD display reads 003 or higher for a good battery. With the probe leads in contact with one another the display should read 0, or else an open circuit is indicated). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitchell (US 4804908) hereinafter ‘Mitchell’, and further in view of Li (US 20100013511), hereinafter ‘Li’. Regarding Claim 1, Mitchell discloses a tester for measuring electrical properties (Abstract A digital voltage and continuity test instrument; AC, DC and continuity test functions are provided with the AC and DC test modes including auto-zeroing), comprising: a user interface (Abstract he display provides a reading proportionate to the battery voltage level of the instrument, Fig. 1, display 12 and Fig. 1 switch 16 for selections between various modes); a measurement circuit (Clm 1 first and second electrical probes including leads for probing circuits to be tested) including a to-be-tested component and a signal source (Abstract with the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument); configured to conduct a self-test on a test path, formed by coupling the to-be-tested component between the signal source and a terminal of the tester (Clm 1 an analog to digital converter for receiving a voltage differential and driving said display according to the magnitude of the received differential; and (f) a slide switch for applying the output of said AC rectifier to said converter in the AC test mode, for applying the output of said resistive divider network to said converter in the DC test mode and for applying a battery supplied voltage bias proportional to said battery voltage between said probes in said self-test mode to cause said converter and LCD to display a battery level indication proportional to said battery voltage when said probes are open circuit indicating battery condition and to cause said converter to drive said LCD top a zero display state when said probes are shortened together indicating good probe continuity; Col. 4 Lines 11-19), in response to a user input from the user interface (Fig 1, slide switch 16; Col. 2 lines 55-59). Mitchell fails to explicitly disclose a controller coupled to the user interface and the measurement circuit. However Li discloses a multimeter comprising a controller for the benefit of controlling switches to different circuit configurations to output terminals of protection circuit, determining the type of DUT for a measure mode to be activated, performing measurements according to the type of DUT, and transmitting the result of measurement to the data processing circuit for transferring the result of measurement into value (Para [0031]). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide the multimeter comprising a controller coupled to the user interface and the measurement circuit for the benefit of controlling switches to different circuit configurations to output terminals of protection circuit, determining the type of DUT for a measure mode to be activated, performing measurements according to the type of DUT, and transmitting the result of measurement to the data processing circuit for transferring the result of measurement into value with a final result of the measurement displayed on a display as taught by Li in Para [0031]. Regarding Claim 2, Mitchell in view of Li further disclose wherein the controller is configured to detect an electrical property at a node in the test path adjacent to the to-be-tested component and determine a result of the self-test based on the electrical property at the node (Col. 3, Line 50-Col. 4, Line 9 use of leads to establish test voltage in circuit). Regarding Claim 3, Mitchell in view of Li further disclose wherein the node is coupled to the controller through an analog-to-digital converter, which is coupled to at least one resistor in series (Fig. 1, circuit comprising circuit 100, controller 20 which controls switches 20 (Para [0031] Meantime the controller 10 controls the switch 20, performs measurement according to the type of DUT, and transmits the result of measurement to the data processing circuit 50 for transferring the result of measurement into value, wherein the measurement unit in the present invention is composed of an AD/DA converter 40, a data processing circuit 50, and a range control unit 90; finally, the result of measurement is displayed on the display 60), Para [0033] the switch 20 and electric switches SW101/SW103 are connected to three output terminals in the protection circuit 100, T1/T2/T3, according to different circuit configurations in keeping with different checking phases, as shown in FIGS. 4-9). Regarding Claim 4, Mitchell in view of Li further disclose wherein the signal source is a DC signal source, and the to-be-tested component includes a resistive voltage divider circuit; and wherein the node is between two resistors of the resistive voltage divider circuit (Abstract With the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument. The electrical test circuitry includes a resistive divider network connected between the test probes, battery as DC signal source; Col. 1, Lines 67-Col. 2, Line 13). Regarding Claim 5, Mitchell further discloses wherein the signal source is a DC signal source (Abstract, Clm 1, test of battery). Mitchell fails to explicitly disclose the to-be-tested component includes a positive temperature coefficient (PTC) circuit; and wherein the PTC circuit includes a PTC thermistor and a resistor coupled in series. Li discloses a multimeter comprising a protection circuit for protecting the measuring device wherein the protection circuit includes a PTC positive temperature coefficient thermistor coupled to a resistor (Fig. 2, R.sub.PCT and R2) for the benefit of protecting the terminals from being damaged under measure mode for measuring voltage and current. A series connection can be considered with switches closed/on (Para [0032]). Applicant fails to disclose an exact benefit of the PTC thermistor and a resistor coupled in series and further discloses the series coupling of the resistor as optional (Applicants Para [0037] disclosing if only the PTC thermistor PTC of the PTC circuit 242 is a to-be-tested component, the test path 240 may be formed to include only the PTC but not the resistor R1 of the PTC circuit 242). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine the teachings of Mitchell and provide the multimeter comprising a protection circuit with its respective elements as disclosed by Li for protecting the measuring device from being damaged under measure mode when measuring voltage and current. Regarding Claim 6, Mitchell in view of Li further disclose wherein the test path is configured to short-circuit an input terminal and a common terminal of the tester, and wherein the test path includes a switch, to be coupled between the input terminal and the common terminal (Clm 1 applying a battery supplied voltage bias proportional to said battery voltage between said probes in said self-test mode to cause said converter and LCD to display a battery level indication proportional to said battery voltage when said probes are open circuit indicating battery condition and to cause said converter to drive said LCD top a zero display state when said probes are shortened together indicating good probe continuity.), in view of Li disclosing switch controllable by the controller (Para [0031] Li discloses a multimeter comprising a controller for the benefit of controlling switches to different circuit configurations to output terminals of protection circuit). Regarding Claim 7, Mitchell in view of Li further disclose wherein the to-be-tested component includes an RC series circuit, and the signal source is an AC signal source (Mitchell in Abstract digital voltage and continuity test instrument for use by electricians is disclosed. AC, DC and continuity test functions are provided with the AC and DC test modes; Col. 3, lines 62-66). Regarding Claim 8, Mitchell in view of Li further disclose wherein the terminal of the tester is a reference node in the tester, and the test path includes a resistive voltage divider circuit coupled between the RC series circuit and the reference node (Mitchell in Col. 3, Lines 59-Col 4, Line10). Regarding Claim 9, Mitchell in view of Li further disclose wherein the resistive voltage divider circuit includes a first resistor adjacent to the RC series circuit and a second resistor further from the RC series circuit than the first resistor, and wherein a first resistance value of the first resistor is greater than a second resistance value of the second resistor (Mitchell in Col. 3, Lines 59-Col 4, Line10 with respective values shown in Fig. 7). Regarding Claim 11, Mitchell in view of Li further disclose the signal source is configured to generate a first voltage signal (Mitchell in Abstract with the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument), and the controller is configured to read a second voltage signal at the terminal of the tester (Li in Para [0031]). Mitchell and Li fail to explicitly disclose wherein the to-be-tested component is located on a semiconductor chip, outside of the signal source. However it would have been obvious to one having ordinary skill in the art before the effective date where the claimed differences involved to the substitution of interchangeable or replaceable equivalents of a component to be tested such, as a semiconductor chip, and the reason for the selection of one equivalent for another was not to solve an existent problem, such substitution has been judicially determined to have been obvious. In re Ruff, 118, USPQ, 343 (CCPA 1958). This supporting is based on recognition that the claimed difference exist not a result of an attempt by applicant to solve a problem but merely amounts to selection of expedients known to the artisan of ordinary skill as design choices. Regarding Claims 12 and 13, Mitchell in view of Li discloses the signal source is an AC signal source or of Clm 13 (Mitchell in Abstract digital voltage and continuity test instrument for use by electricians is disclosed. AC, DC and continuity test functions are provided with the AC and DC test modes; Col. 3, lines 62-66), wherein the AC signal source is configured to apply the first voltage signal (Mitchell in Abstract with the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument; AC, DC and continuity test functions are provided with the AC and DC test modes) and of Clm 13 wherein the DC signal source is configured to apply the first voltage signal (Mitchell in Abstract with the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument; AC, DC and continuity test functions are provided with the AC and DC test modes), which is coupled to the controller through an analog-to-digital converter. (Fig. 1, circuit comprising circuit 100, controller 20 which controls switches 20 (Para [0031] Meantime the controller 10 controls the switch 20, performs measurement according to the type of DUT, and transmits the result of measurement to the data processing circuit 50 for transferring the result of measurement into value, wherein the measurement unit in the present invention is composed of an AD/DA converter 40, a data processing circuit 50, and a range control unit 90; finally, the result of measurement is displayed on the display 60) Mitchell and Li fail to explicitly disclose wherein the to-be-tested component includes an RMS-to-DC converter, with a signal applied directly to the RMS-to-DC converter and of Clm 13 wherein the to-be-tested component includes an analog-to-digital converter with a signal applied directly to the analog-to-digital converter. However it would have been obvious to one having ordinary skill in the art before the effective date where the claimed differences involved to the substitution of interchangeable or replaceable equivalents of a component to be tested, such as a well-known RMS-to-DC converter within a multimeter or of Clm 13 the to-be-tested component includes an analog-to-digital converter, and the reason for the selection of one equivalent for another was not to solve an existent problem, such substitution has been judicially determined to have been obvious. In re Ruff, 118, USPQ, 343 (CCPA 1958). This supporting is based on recognition that the claimed difference exist not a result of an attempt by applicant to solve a problem but merely amounts to selection of expedients known to the artisan of ordinary skill as design choices. Regarding Claims 18 and 19, Mitchell discloses the method according to Claim 14 above. Mitchell further discloses wherein the signal source is a current source (Abstract A digital voltage and continuity test instrument for use by electricians is disclosed. AC, DC and continuity test functions are provided with the AC and DC test modes), the electrical property is a voltage (Abstract With the probes open circuit in the continuity mode the display provides a reading proportionate to the battery voltage level of the instrument). Mitchell fails to explicitly disclose computing another electrical property based on the electrical property; and comparing the another electrical property with a stored electrical property information. Li discloses a multimeter which comprises measuring functions and comparing voltages through a plurality of comparison circuits for the benefit of determining a device under test and of Clm 19, determining whether DUT is a large or small resistor (Abstract; Para [0012]). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide the multimeter which computes another electrical property based on the electrical property; and comparing the another electrical property with a stored electrical property information for the benefit of determining a device under test as taught by Li in the Abstract and in Para [0012]. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitchell (US 4804908), in view of Li (US 20100013511), hereinafter ‘Li’, and further in view of Jackson et al. (US 4821217), hereinafter ‘Jackson’. Regarding Claim 10, Mitchell further discloses wherein the controller is configured to detect an electrical property at a node between the first resistor and the second resistor (Col. 3, Lines 50-Col. 4, Line 10; Fig. 2 terminals 100 and 101 connect to lead wires to establish test). Mitchell and Li fail to explicitly disclose an RMS-to-DC converter being coupled between the node and the controller. Jackson discloses a self-test module to include digital multimeters with a controller and programmable measurement function that comprises true RMS DC voltage measurements for the benefit of performing diagnostic self-test which check both the digital and analog circuitry in the multimeter (Col. 14, Lines 25-39). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine the teachings of Mitchell in view of Li to include an RMS-to-DC converter being coupled between the node and the controller the benefit of performing diagnostic self-test which check both the digital and analog circuitry in the multimeter as taught by Jackson in Col. 14, Lines 25-39. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitchell (US 4804908) hereinafter ‘Mitchell’, and further in view of Aikins et al. (US 8336190), hereinafter ‘Aikins’. Regarding Claim 16, Mitchell fails to explicitly disclose prompting a user to short a first test lead coupled to a measurement terminal of the tester to a second test lead coupled to a common terminal of the tester for completing the self-test. Aikins discloses a method of calibrating a test instrument and a set of leads having proximal ends coupled with the test instrument, the method including: shorting distal ends of the set of leads during the calibrating resulting in zeroing the test instrument during the shorting (Clm 1) for the benefit of measuring continuity accurately prior to making a measurement (Col. 1, Lines 29-45). Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine the teachings of Mitchell in view of Aikins for the benefit of measuring continuity accurately prior to making a measurement as taught by Aikins in Col. 1, Lines 29-45. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALESA ALLGOOD whose telephone number is (571)270-5811. The examiner can normally be reached M-F 7:30 AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALESA ALLGOOD/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Mar 04, 2024
Application Filed
Nov 23, 2025
Non-Final Rejection — §102, §103
Mar 03, 2026
Interview Requested
Mar 17, 2026
Applicant Interview (Telephonic)
Mar 17, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+18.3%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 641 resolved cases by this examiner. Grant probability derived from career allow rate.

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