DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 7/13/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the structural relationship between the semiconductor layer, the first conductor, and the contact regions. The device being a 3D memory device, all the elements are understood to extend in three mutually orthogonal directions. However, claim 1 fails to establish the disposition of each elements relative to the other, such that they can be anywhere within the device.
Claims 2-10 are rejected based on their dependency on claim 1.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the structural relationship between the semiconductor layer, the first conductor, and the contact regions. The device being a 3D memory device, all the elements are understood to extend in three mutually orthogonal directions. However, claim 11 fails to establish the disposition of each elements relative to the other, such that they can be anywhere within the device.
Claims 12-20 are rejected based on their dependency on claim 11.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nikaki US 20150069499 A1 (hereinafter referred to as Nikaki).
Regarding claim 1, Nikaki teaches
A storage device (“memory cell array 1” para. 0075 FIG. 3) comprising:
a plurality of memory cell regions (“blocks” para. 0055 FIG. 1), each of the plurality of memory cell regions being provided with a semiconductor layer (“back gate BG” comprising silicon doped with boron, para. 0091 FIG. 2) extending in a first direction (“back gate BG” extends in X, Y, Z) and a pillar (“columnar parts CL” para. 0030 FIG. 1-3) having a side surface in contact with the semiconductor layer and extending in a second direction (“columnar parts CL” have a side surface in contact with “back gate BG”);
a first conductor (“tier selecting section 2” with “electrode layers WL” para. 0054 FIG. 1-3) provided with a first portion (“tier selecting section 2”) and a plurality of second portions (“electrode layers WL”), one of which is in contact with the semiconductor layer (“world line layer WL” is in electrical contact with “back gate BG”), the first portion extending in the first direction (“tier selecting portion extends in X, Y, Z), and the plurality of the second portions extending in a third direction (“electrode layers WL” extend in X, Y, Z) and connected to the first portion; and
a plurality of contact regions (portion “region 100” para. 0058 FIG. 1-2), each of the plurality of contact regions being provided with a plurality of contacts (“plugs 80a-80f” para. 0071 FIG. 2 and 5) extending in the second direction, wherein
a plurality of groups is arranged in the first direction when viewed in the second direction, each of groups including one of the plurality of memory cell regions, one of the plurality of second portions, and one of the plurality of contact regions, which are arranged in the first direction when viewed in the second direction (groups can be defined that include a “block” with an “electrode layer WL” and a portion of “region 100” as seen in FIG. 2).
Regarding claim 2, Nikaki teaches the storage device according to claim 1, wherein one of the plurality of contacts is in contact with the first conductor in each of the plurality of groups (“plug 80b” is in contact with the “electrode layer WL” that has “contact part 62b” as shown in FIG. 2).
Regarding claim 3, Nikaki teaches the storage device according to claim 1, wherein one of the plurality of contacts has a side surface in contact with the first conductor in each of the plurality of groups (“Lower part 82” of “plug 80b” is in contact with the end surface of the “contact part 62b”, FIG. 2 and 5 para. 0073)
Regarding claim 9, Nikaki teaches the storage device according to claim 1, wherein the pillar includes: a fourth conductor (32) having a cylindrical shape and extending in the second direction; a first insulator (33,34?) extending in the second direction and surrounding the fourth conductor; a second insulator (35) extending in the second direction and surrounding the first insulator; and a third insulator (36) extending in the second direction, surrounding the second insulator, and being in contact with the semiconductor layer.
the pillar includes: a fourth conductor (“channel body 20” made of doped silicon, para. 0036 FIG. 4) having a cylindrical shape (“channel body 20” has a tubular shape as shown in FIG. 1-3, para. 0038) and extending in the second direction (“channel body 20” extends in the X, Y, and Z directions);
a first insulator (“tunnel film 33” para. 0037) extending in the second direction and surrounding the fourth conductor;
a second insulator (“charge storage film 32” para. 0037) extending in the second direction and surrounding the first insulator; and
a third insulator (“block film 31” para. 0037) extending in the second direction, surrounding the second insulator, and being in contact with the semiconductor layer (“block film 31” is in contact with the “electrode layers WL”, para.0039).
Regarding claim 10, Nikaki teaches the storage device according to claim 9, wherein the second insulator is a charge storage layer (“charge storage film 32” stores charge, para. 0040).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nikaki, as applied to claim 1, in view of Liu US 20200350287 A1 (hereinafter referred to as Liu).
Regarding claim 4, Nikaki teaches the storage device according to claim 1 but fails to teach further comprising: a first sense amplifier unit region (SAUR) provided with a sense amplifier unit (SAU); a first transistor having a first end connected to one of the plurality of contacts and a second end; and a second conductor having a third end connected to the second end of the first transistor and a fourth end located in the first sense amplifier unit region when viewed in the second direction.
Nevertheless, Liu teaches
a first sense amplifier unit region (SAUR) (“device layer 310”, para. 0045) provided with a sense amplifier unit (SAU) (the circuits made of “transistors 316” in “device layer 310” form sense amplifiers, para. 0045);
a first transistor (“transistor 316” on the left as marked in annotated FIG. 3) having a first end (left contact of “transistor 316”) and a second end (right contact of “transistor 316”); and
a second conductor (highlighted wiring of “interconnect layer 322”) having a third end (left side of wiring) and a fourth end located in the first sense amplifier unit region when viewed in the second direction (right portion of wiring is in the sense amplifier as would be seen from above).
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Nakaki and Liu teach 3D memory devices. Liu teaches how each peripheral circuit of “high-speed logic transistors 312” or “sensing & controller circuit 314” includes a plurality of “transistors 316” forming any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device 300 including, but not limited to, a sense amplifier (para. 0045). It is understood that the circuits formed of “transistors 316” can be sense amplifiers. As taught in Sato US 20210305268 A1: a sense amplifier detects and amplifies data read from memory cell transistors to the bit line; the sense amplifier then temporarily retains read data read from the memory cell transistors and transfers the read data to the input/output circuit. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the sense amplifier units can be used to sense, amplify, and send the memory cell data in “memory cell region 1”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device in Nikaki with the sense amplifier unit region taught in Liu. Sense amplifier units in the region amplify a sensed data in the memory cell region and send it to input and output circuitry.
However, Nakaki, modified by Liu fails to expressly teach the first end connected to one of the plurality of contacts, the second conductor having the third end connected to the second end of the first transistor.
Nevertheless, the “interconnect layer 322” is used to transfer signals to and from the “device layer 310” (para. 0047). “3D NAND memory strings 338” are connected to “device layer 310” through “interconnect layers 332 and 322” (para. 0058). Furthermore, “Interconnect layers 332 and 322” are connected to the “contacts 354” through what appears as a contact plug that traverses the thickness of the memory cell region so that the “device layer 310” can connect to outside circuits (para. 0058 FIG. 3). In other words, there is electrical connection between a “transistor 316” and the contact plug that connects with “contact 354” and it is reasonable to expect that signals from “transistor 316” pass through wiring in “interconnect layer 322”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that an end of “transistor 316” electrically connects with a contact plug through wiring in “interconnect layer 322” so that “transistor 316” can communicate with the outside.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that second end is connected to one of the plurality of contacts through the second conductor. Connection to the outside can thus be established for the transistor.
Regarding claim 5, Nikaki modified by Liu teach the storage device according to claim 4, wherein the first transistor is spaced apart in the second direction with respect to the plurality of contacts (“transistor 316” is below the contact plug as seen from the side view presented in FIG. 3), the second conductor is spaced apart in the second direction with respect to the first transistor (“transistor 316” is below the wiring of “interconnect layer 322”), and the sense amplifier unit is spaced apart in the second direction with respect to the second conductor (the sense amplifier consisting of the “transistors 316” are in “device layer 310” while the wiring of “interconnect layer 322” is above).
Regarding claim 6, Nikaki modified by Liu teach the storage device according to claim 1 but fail to teach wherein N first conductors including the first conductor and N sense amplifier unit regions are provided, where N is an integer of 2 or more.
Nevertheless, the examiner understands there are a plurality of stacked “tier selecting section 2” with “electrode layers WL” since “electrode layers WL” are shown stacked in FIG. 2 of Nakaki. Furthermore, although only one “tier selecting section 2” with “electrode layers WL” is shown, it is obvious that these structures can be duplicated and disposed alongside each other on “substrate 10”. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144 VI.B), such that different “tier selecting regions 2” and “electrode layers WL”, and thus “memory cell arrays 1”, can be arranged along the X direction. This will also increase the data storage capacity of the device. Liu teaches how each peripheral circuit of “high-speed logic transistors 312” or “sensing & controller circuit 314” includes a plurality of “transistors 316” forming any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device 300 including, but not limited to, a sense amplifier (para. 0045). It is understood that the circuits formed of “transistors 316” can be sense amplifiers. As taught in Sato US 20210305268 A1: a sense amplifier detects and amplifies data read from memory cell transistors to the bit line; the sense amplifier then temporarily retains read data read from the memory cell transistors and transfers the read data to the input/output circuit. It is reasonable to expect that a plurality of sense amplifier units is needed in each “memory cell array 1” for sensing the memory cell data. Each group of sense amplifier units formed by “transistors 316” working on corresponding “memory cell array 1” can be considered a sense amplifier unit region. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that each “memory cells array 1” will have a region of sense amplifier units for data sensing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught in Nakaki with the sense amplifier unit regions as taught in Liu. Sense amplifier units can sense, amplify, and transmit data from the memory cells. Each memory cell region has a corresponding sense amplifier unit region consisting of a group of sense amplifier units acting on the memory cells.
Regarding claim 7, Nikaki modified by Liu teach the storage device according to claim 6, wherein the first portion of each first conductor has fifth and sixth ends in the first direction (though the exact end is not shown, each “tier selecting section 2” with “electrode layers WL” has ends along the Y direction as marked in annotated FIG. 1 below), and the N sense amplifier unit regions are arranged along the first direction when viewed in the second direction in a region between an imaginary first straight line including the fifth end and an imaginary second straight line including the sixth end (since the “transistors 316” are disposed in the “first semiconductor structure 302” under the memory cells in “second semiconductor structure 304”, and therefore under the “memory cells arrays 1”, the sense amplifier unit regions are under each corresponding “memory cell array 1”).
Regarding claim 8, Nikaki modified by Liu teach the storage device according to claim 7 but fails to teach further comprising: a third conductor aligned in the first direction with the first conductor, separated from the first conductor, and provided with a third portion extending in the first direction; and M second sense amplifier unit regions, where M is an integer of 2 or more, wherein each of the M second sense amplifier unit regions is provided with the sense amplifier unit, the third portion of the third conductor has seventh and eighth ends in the first direction, and the M second sense amplifier unit regions are arranged in the first direction when viewed in the second direction in a region between an imaginary third straight line including the seventh end and an imaginary fourth straight line including the eighth end.
Nevertheless, there are N “tier selecting section 2” with “electrode layers WL” arranged in the X direction. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144 VI.B), such that different “tier selecting regions 2” and “electrode layers WL”, and thus “memory cell arrays 1”, can be arranged along the Y direction as well to further increase the data storage capacity. As with the “memory cell regions 1” arranged in X, a plurality of sense amplifier units is needed in each “memory cell array 1” for sensing the memory cell data. The “memory cell regions 1” arranged in Y will also have corresponding sense amplifier unit regions. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that more “memory cell regions 1” can be arranged along the Y direction and each “memory cells array 1” will have a region of sense amplifier units for data sensing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further duplicate the memory cell regions along the Y direction. More data can be stored and each memory cell region has a corresponding sense amplifier unit region consisting of a group of sense amplifier units to amplify the stored data.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakaki, in view of Liu US 20200350287 A1 (hereinafter referred to as Liu).
Regarding claim 11, Nikaki teaches
A storage device (“semiconductor memory device” para. 0014-16 FIG. 1-5) comprising:
a first chip (“semiconductor memory device”)
wherein the first chip includes:
a plurality of memory cell regions (“blocks” in “memory cell array region” para. 0055 FIG. 1), each of the plurality of memory cell regions being provided with a semiconductor layer (“back gate BG” comprising silicon doped with boron, para. 0091 FIG. 2) extending in a first direction (“back gate BG” extends in X, Y, Z) and a pillar (“columnar parts CL” para. 0030 FIG. 1-3) having a side surface in contact with the semiconductor layer and extending in a second direction (“columnar parts CL” have a side surface in contact with “back gate BG”);
a first conductor (“tier selecting section 2” with “electrode layers WL” para. 0054 FIG. 1-3) provided with a first portion (“tier selecting section 2”) and a plurality of second portions (“electrode layers WL”), one of which is in contact with the semiconductor layer (“world line layer WL” is in electrical contact with “back gate BG”), the first portion extending in the first direction (“tier selecting portion extends in X, Y, Z), and the plurality of the second portions extending in a third direction (“electrode layers WL” extend in X, Y, Z) and connected to the first portion; and
a plurality of contact regions (portion “region 100” para. 0058 FIG. 1-2), each of the plurality of contact regions being provided with a plurality of contacts (“plugs 80a-80f” para. 0071 FIG. 2 and 5) extending in the second direction, wherein
a plurality of groups is arranged in the first direction when viewed in the second direction, each of groups including one of the plurality of memory cell regions, one of the plurality of second portions, and one of the plurality of contact regions, which are arranged in the first direction when viewed in the second direction (groups can be defined that include a “block” with an “electrode layer WL” and a portion of “region 100” as seen in FIG. 2).
However, Nakaki fails to teach the first chip having a plurality of first bonding pads; and a second chip having a plurality of second bonding pads that are respectively bonded to the plurality of first bonding pads.
Nevertheless, Liu teaches
the first chip (“second semiconductor structure 304” para. 0043 FIG. 3) having a plurality of first bonding pads (“bonding contacts 330” para. 0049); and
a second chip (“first semiconductor structure 302” para. 0048) having a plurality of second bonding pads (“bonding contacts 324”, para. 0048) that are respectively bonded to the plurality of first bonding pads.
Nakaki and Liu teaches semiconductor memory devices. The device in Nakaki has a circuit on the surface of “substrate 10” for controlling the “memory cell array 1” (para. 0023). “Bit lines BL” and “source line SL” connect to the peripheral circuit through “upper layer interconnection 111” and “plug 112” that traverse the height of the memory cell region (Nakaki para. 0077 FIG. 2). Meanwhile, the “3D NAND memory strings 338” in Liu connect to “bonding contacts 326” that are on a side of the “second semiconductor structure 304” closer to where “interconnect layer 332” is disposed (Liu para. 0058). Instead of making a path down to the opposite side of the memory cell region like in Nakaki, Liu forms “bonding contacts 330” on the same side of the memory cell array as the “interconnect layer 332” so that they can bond to the “first semiconductor structure 302”. This is a simpler and circuit path between the memory cell array and the peripheral circuit. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the signal paths between the memory cell array and the peripheral circuit can be made such that the inputs and outputs face each other instead of forming “plug 112” to connect “upper layer interconnection 111” with the circuitry on “substrate 10” on the opposite side.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device in Nakaki with the first and second chips as taught in Liu. A simplified circuit path between the memory cell array and the peripheral circuit can be achieved.
Regarding claim 12, Nikaki, in view of Liu, teach the storage device according to claim 11, wherein one of the plurality of contacts is in contact with the first conductor in each of the plurality of groups (“plug 80b” is in contact with the “electrode layer WL” that has “contact part 62b” as shown in FIG. 2).
Regarding claim 13, Nikaki, in view of Liu, teach the storage device according to claim 11, wherein one of the plurality of contacts has a side surface in contact with the first conductor in each of the plurality of groups (“Lower part 82” of “plug 80b” is in contact with the end surface of the “contact part 62b”, FIG. 2 and 5 para. 0073).
Regarding claim 14, Nikaki, in view of Liu, teach the storage device according to claim 11, wherein the second chip includes a first sense amplifier unit region (SAUR) (“device layer 310”, para. 0045) provided with a sense amplifier unit (SAU) (the circuits made of “transistors 316” in “device layer 310” form sense amplifiers, para. 0045);
the first chip includes a first transistor (“transistor 316” on the left as marked in annotated FIG. 3) having a first end (left contact of “transistor 316”) and a second end (right contact of “transistor 316”); and
a second conductor (highlighted wiring of “interconnect layer 322”) having a third end (left side of wiring) and a fourth end located in the first sense amplifier unit region when viewed in the second direction (right portion of wiring is in the sense amplifier as would be seen from above).
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However, Nakaki, modified by Liu fails to expressly teach the first end connected to one of the plurality of contacts, the second conductor having the third end connected to the second end of the first transistor.
Nevertheless, the “interconnect layer 322” is used to transfer signals to and from the “device layer 310” (para. 0047). “3D NAND memory strings 338” are connected to “device layer 310” through “interconnect layers 332 and 322” (para. 0058). Furthermore, “Interconnect layers 332 and 322” are connected to the “contacts 354” through what appears as a contact plug that traverses the thickness of the memory cell region so that the “device layer 310” can connect to outside circuits (para. 0058 FIG. 3). In other words, there is electrical connection between a “transistor 316” and the contact plug that connects with “contact 354” and it is reasonable to expect that signals from “transistor 316” pass through wiring in “interconnect layer 322”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that an end of “transistor 316” electrically connects with a contact plug through wiring in “interconnect layer 322” so that “transistor 316” can communicate with the outside.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that second end is connected to one of the plurality of contacts through the second conductor. Connection to the outside can thus be established for the transistor.
Regarding claim 15, Nikaki modified by Liu teach the storage device according to claim 14, wherein the first transistor is spaced apart in the second direction with respect to the plurality of contacts (“transistor 316” is below the contact plug as seen from the side view presented in FIG. 3), the second conductor is spaced apart in the second direction with respect to the first transistor (“transistor 316” is below the wiring of “interconnect layer 322”), and the sense amplifier unit is spaced apart in the second direction with respect to the second conductor (the sense amplifier consisting of the “transistors 316” are in “device layer 310” while the wiring of “interconnect layer 322” is above).
Regarding claim 16, Nikaki modified by Liu teach the storage device according to claim 11 but fail to teach wherein N first conductors including the first conductor and N sense amplifier unit regions are provided, where N is an integer of 2 or more.
Nevertheless, the examiner understands there are a plurality of stacked “tier selecting section 2” with “electrode layers WL” since “electrode layers WL” are shown stacked in FIG. 2 of Nakaki. Furthermore, although only one “tier selecting section 2” with “electrode layers WL” is shown, it is obvious that these structures can be duplicated and disposed alongside each other on “substrate 10”. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144 VI.B), such that different “tier selecting regions 2” and “electrode layers WL”, and thus “memory cell arrays 1”, can be arranged along the X direction. This will also increase the data storage capacity of the device. Liu teaches how each peripheral circuit of “high-speed logic transistors 312” or “sensing & controller circuit 314” includes a plurality of “transistors 316” forming any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device 300 including, but not limited to, a sense amplifier (para. 0045). It is understood that the circuits formed of “transistors 316” can be sense amplifiers. As taught in Sato US 20210305268 A1: a sense amplifier detects and amplifies data read from memory cell transistors to the bit line; the sense amplifier then temporarily retains read data read from the memory cell transistors and transfers the read data to the input/output circuit. It is reasonable to expect that a plurality of sense amplifier units is needed in each “memory cell array 1” for sensing the memory cell data. Each group of sense amplifier units formed by “transistors 316” working on corresponding “memory cell array 1” can be considered a sense amplifier unit region. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that each “memory cells array 1” will have a region of sense amplifier units for data sensing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device taught in Nakaki with the sense amplifier unit regions as taught in Liu. Sense amplifier units can sense, amplify, and transmit data from the memory cells. Each memory cell region has a corresponding sense amplifier unit region consisting of a group of sense amplifier units acting on the memory cells.
Regarding claim 17, Nikaki modified by Liu teach the storage device according to claim 16, wherein the first portion of each first conductor has fifth and sixth ends in the first direction (though the exact end is not shown, each “tier selecting section 2” with “electrode layers WL” has ends along the Y direction as marked in annotated FIG. 1 below), and the N sense amplifier unit regions are arranged along the first direction when viewed in the second direction in a region between an imaginary first straight line including the fifth end and an imaginary second straight line including the sixth end (since the “transistors 316” are disposed in the “first semiconductor structure 302” under the memory cells in “second semiconductor structure 304”, and therefore under the “memory cells arrays 1”, the sense amplifier unit regions are under each corresponding “memory cell array 1”).
Regarding claim 18, Nikaki modified by Liu teach the storage device according to claim 17 but fails to teach further comprising: a third conductor aligned in the first direction with the first conductor, separated from the first conductor, and provided with a third portion extending in the first direction; and M second sense amplifier unit regions, where M is an integer of 2 or more, wherein each of the M second sense amplifier unit regions is provided with the sense amplifier unit, the third portion of the third conductor has seventh and eighth ends in the first direction, and the M second sense amplifier unit regions are arranged in the first direction when viewed in the second direction in a region between an imaginary third straight line including the seventh end and an imaginary fourth straight line including the eighth end.
Nevertheless, there are N “tier selecting section 2” with “electrode layers WL” arranged in the X direction. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144 VI.B), such that different “tier selecting regions 2” and “electrode layers WL”, and thus “memory cell arrays 1”, can be arranged along the Y direction as well to further increase the data storage capacity. As with the “memory cell regions 1” arranged in X, a plurality of sense amplifier units is needed in each “memory cell array 1” for sensing the memory cell data. The “memory cell regions 1” arranged in Y will also have corresponding sense amplifier unit regions. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that more “memory cell regions 1” can be arranged along the Y direction and each “memory cells array 1” will have a region of sense amplifier units for data sensing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further duplicate the memory cell regions along the Y direction. More data can be stored and each memory cell region has a corresponding sense amplifier unit region consisting of a group of sense amplifier units to amplify the stored data.
Regarding claim 19, Nikaki, in view of Liu, teach the storage device according to claim 11, wherein
the pillar includes: a fourth conductor (“channel body 20” made of doped silicon, para. 0036 FIG. 4) having a cylindrical shape (“channel body 20” has a tubular shape as shown in FIG. 1-3, para. 0038) and extending in the second direction (“channel body 20” extends in the X, Y, and Z directions);
a first insulator (“tunnel film 33” para. 0037) extending in the second direction and surrounding the fourth conductor;
a second insulator (“charge storage film 32” para. 0037) extending in the second direction and surrounding the first insulator; and
a third insulator (“block film 31” para. 0037) extending in the second direction, surrounding the second insulator, and being in contact with the semiconductor layer (“block film 31” is in contact with the “electrode layers WL”, para.0039).
Regarding claim 20, Nikaki, in view of Liu, teach the storage device according to claim 19, wherein the second insulator is a charge storage layer (“charge storage film 32” stores charge, para. 0040).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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