DETAILED ACTION
This action is responsive to the election received on 08/03/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figure 1) in the reply filed on 08/03/2026 is acknowledged. Claim(s) 15 and 16 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species based on applicants remarks provided with the above cited election, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in Japan on 03/22/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/04/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the second plate-shaped structure is disposed between the first pillar structure array and the dummy pillar structure array" in the final two lines of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 11 depends on claim 1 and only appears to provide antecedent basis for a pillar structure array (claim 1, line 3) while a first pillar structure array (claim 2, line 3) is not introduced until claim 2. Thus it is unclear if claim 11 is intended to be dependent on claim 2 or if claim 1 is referring to the pillar structure array as a whole and the use of the word first is a typo. Therefore claim 11 is rejected under 35 U.S.C. 112(b) for a lack of clear antecedent basis. For the purposes of this examination, claim 11 will be interpreted to read as dependent on claim 2 to provide sufficient antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0203875 A1; Kim et al.; 06/2024; (“Kim”).
Regarding Claim 1. Kim discloses A semiconductor memory device (#100, Figures 1-3C, semiconductor device) comprising:
a stacked body (#130/#120 stack, Figure 2A) including a plurality of conductive layers (#130s, Figure 2A, gate electrodes) stacked in a first direction (z-direction, Figure 2, #130s are stacked in the z-direction);
a pillar structure array (#CH and #DCHs not on #US, Figures 1-3C, array of various pillar structures) including a plurality of pillar structures each extending in the first direction in the stacked body (Figures 2A, 2B, and 2C, the pillar structures all extend in the z-direction through the stack), the plurality of pillar structures being arranged in a second direction intersecting the first direction and a third direction intersecting the first and second directions (Figure 1, the plurality of pillar structures are arranged in a second x-direction and a third intersecting y-direction intersecting the z-direction), the plurality of pillar structures including a plurality of first pillar structures (#CH), each of which is a part of a string of memory cell transistors (Figures 2B and 3C, [0040] and [0031]-[0032], channel structures of vertical memory cell transistor string);
a first plate-shaped structure (#US horizontal portion extending through line III-III’, Figure 1, upper isolation region shown to be plate shaped based on Figures 1 and 2A) extending in the first and second directions in the stacked body (Figures 1 and 2A, the identified portion of #US extends in the z and x-directions in the stack), the first plate-shaped structure partitioning the pillar structure array in the third direction (Figure 1, the identified portion of #US partitions the stack at least partially in the y-direction);
a second plate-shaped structure (#US vertical portion to the right of line III-III’, Figure 1, upper isolation region shown to be plate shaped based on Figures 1 and 2A) extending in the first and third directions in the stacked body (Figures 1 and 2A, the second identified portion of #US extends in the z and y-directions in the stack), the second plate-shaped structure being disposed along an end portion of the pillar structure array in the second direction (Figure 1, let the line III-III’ define an end portion of the pillar structure array in the x-direction); and
a support structure (#DCH at the intersection of the two portions of #US, Figure 1, support structure) extending in the first direction in the stacked body and disposed where the first plate-shaped structure and the second plate-shaped structure intersect (Figures 1 and 2A, #DCH at the identified intersection extends in the z-direction in the stacked body where the identified portions of #US intersect).
Regarding Claim 2. Kim discloses The semiconductor memory device according to claim 1, wherein
the pillar structure array (#CH and #DCHs not on #US, Figures 1-3C) includes a first pillar structure array (Figure 1, array of #CHs in the R1 region) including the plurality of first pillar structures (Figure 1, the #R1 region includes the #CH structures) and a second pillar structure array (Figure 1, array of #DCHs not on #US) disposed between the first pillar structure array and the second plate-shaped structure (Figure 1, an array of #DCHs not on #US is located between the #R1 region and the second plate shaped portion of #US extending in the y-direction), the second pillar structure array including a plurality of second pillar structures (Figures 1 and 2A, all #DCHs are pillar structures), each of which is not a part of a string of memory cell transistors (Figure 1, [0051], #DCHs have no electrical functionality).
Regarding Claim 3. Kim discloses The semiconductor memory device according to claim 2, wherein
each of the second pillar structures has a structure different from each of the first pillar structures ([0052], “support structures DCH may have an internal structure different from that of the channel structures CH”).
Regarding Claim 4. Kim discloses The semiconductor memory device according to claim 2, wherein
the support structure is formed with the same material as a material of the plurality of second pillar structures (Figure 1, the #DCH at the corner of the #US portions and the other #DCH structures are formed of the same materials being part of the same array of structures).
Regarding Claim 5. Kim discloses The semiconductor memory device according to claim 2, wherein
the stacked body includes a first stacked portion (#R1, Figures 1 and 2A) and a second stacked portion adjacent to the first stacked portion in the second direction (Figure 1, portion of #R2 to the left of the second plate-shaped portion of #US which is adjacent to #R1),
the plurality of first pillar structures extend in the first direction in the first stacked portion (Figures 1 and 2B, #CHs extend in the z-direction in #R1), and
the plurality of second pillar structures extend in the first direction in the second stacked portion (Figures 1 and 2C, #DCHs not on #US extend in the z-direction in the portion of #R2 to the left of the third plate-shaped portion of #US and adjacent to #R1).
Regarding Claim 6. Kim discloses The semiconductor memory device according to claim 5, further comprising
a plurality of contacts (#170, Figures 1 and 2C, contact plugs) respectively connected to the plurality of conductive layers in the second stacked portion (Figures 1 and 2C, #170s are connected to the plurality f #130s in the second stacked portion).
Regarding Claim 7. Kim discloses The semiconductor memory device according to claim 6, wherein
a first contact of the plurality of contacts is connected to a first conductive layer of the plurality of conductive layers (Figures 1, upper #170 along the line III-III’ which is physically connected to all of the conductive layers #130 including the lowest one), and the first contact extends in the first direction through one or more conductive layers that are located on an upper layer side of the first conductive layer (Figure 2C, #170 extends through a plurality of #130s on an upper side of the lowest #130).
Regarding Claim 8. Kim discloses The semiconductor memory device according to claim 6, wherein
the support structure is formed with the same material as a material of the plurality of contacts ([0052], “DCH each may include a support insulating layer 107 formed of an insulating material. The support insulating layer 107 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride”; Figure 2A, #160, contact insulating layers which may be interpreted as part of the contacts #170, [0071], “contact insulating layers 160 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride”; i.e. both may be formed at least partially with a same insulating material).
Regarding Claim 9. Kim discloses The semiconductor memory device according to claim 6, further comprising
a dummy pillar structure array (Figure 1, array of #DCHs to the right of the second plate-shaped structure) including a plurality of dummy pillar structures (Figure 1, array of #DCHs to the right of the second plate shaped structure are an array of dummy channel structures, see [0051]), each of which extends in the first direction in the stacked body and is not a part of a string of memory cell transistors (Figures 1-3A, #DCHs all extend through the stacked body and serve no electrical purpose according to [0051]), wherein
the second plate-shaped structure is disposed between the second pillar structure array and the dummy pillar structure array (Figure 1, the vertically extending portion of #US adjacent to the line III-III’ is at least partially between the second pillar structure array to its left and the dummy pillar structure array to its right).
Regarding Claim 10. Kim discloses The semiconductor memory device according to claim 9, wherein
the stacked body further includes a third stacked portion adjacent to the second stacked portion in the second direction (Figure 1, portion of #R2 to the right of the second plate-shaped portion of #US which is adjacent to the portion to the left of the second plate-shaped portion of #US), and
each of the dummy pillar structures extends in the first direction in the third stacked portion (Figures 1 and 2C, #DCHs not on #US to the right of the second plate shaped portion extend in the z-direction in the portion of #R2 to the right of the third plate-shaped portion).
Regarding Claim 11. Kim discloses The semiconductor memory device according to claim [[1]] 2, further comprising
a dummy pillar structure array (Figure 1, array of #DCHs to the right of the second plate-shaped structure) including a plurality of dummy pillar structures (Figure 1, array of #DCHs to the right of the second plate shaped structure are an array of dummy channel structures, see [0051]) each of which extends in the first direction in the stacked body and is not a part of a string of memory cell transistors (Figures 1-3A, #DCHs all extend through the stacked body and serve no electrical purpose according to [0051]), wherein
the second plate-shaped structure is disposed between the first pillar structure array and the dummy pillar structure array (Figure 1, the vertically extending portion of #US adjacent to the line III-III’ is at least partially between the first pillar structure array to its left and the dummy pillar structure array to its right).
Regarding Claim 12. Kim discloses The semiconductor memory device according to claim 1, wherein
the support structure is in contact with the stacked body, the first plate-shaped structure, and the second plate-shaped structure (Figures 1 and 2C, the #DCH at the intersection of the two plate shaped structures of #US is in contact with the stacked structure and both of the intersecting plate shaped structures).
Regarding Claim 13. Kim discloses The semiconductor memory device according to claim 1, wherein
the support structure has a pillar shape (Figures 1 and 2C, the #DCH at the intersection of the two plate shaped structures of #US is a pillar shape).
Regarding Claim 14. Kim discloses The semiconductor memory device according to claim 13, wherein
the support structure has a circular pattern when observed from the first direction (Figure 1, the #DCH at the intersection of the two plate shaped structures has a circular pattern when viewed in the top down view of Figure 1).
Regarding Claim 17. Kim discloses The semiconductor memory device according to claim 1, wherein
the stacked body (#130/#120 stack, Figure 2A) includes the plurality of conductive layers (#130s, Figure 2A, gate electrodes) and a plurality of insulation layers (#120, Figure 2A, interlayer insulating layers) alternately stacked in the first direction (Figure 2A, #130s and #120s are alternately stacked in the z-direction).
Regarding Claim 18. Kim discloses A semiconductor memory device (#100, Figures 1-3C, semiconductor device) comprising:
first (#130/#120 stack in the #R1 region, Figures 1 and 2A) and second stacked bodies (Figure 1, portion of #R2 to the left of first vertically extending portion of #US which is adjacent to #R1), each including a plurality of conductive layers (#130s, Figure 2A, gate electrodes) and a plurality of insulating layers (#130s, Figure 2A, gate electrodes) (#120, Figure 2A, interlayer insulating layers) alternately stacked in a first direction (Figure 2A, #130s and #120s are alternately stacked in a z-direction);
a plurality of memory pillars (#CHs, Figures 1-3C, array of channel structures) each including a semiconductor layer (#140, Figure 3C, channel layer made of semiconductor material according to [0047]) and extending in the first direction in the first stacked body (Figures 1 and 3C, #140 extends in the z-direction in the #R1 region), the plurality of memory pillars arranged in a second direction intersecting the first direction and a third direction intersecting the first and second directions (Figure 1, the plurality of #CHs are arranged in a second x-direction and a third intersecting y-direction intersecting the z-direction);
a plurality of insulating pillars (#DCHs not on #US, Figures 1 and 2A, dummy channel support structures made of insulating material according to [0052]) each extending in the first direction in the second stacked body (Figures 1 and 2C, #DCHs not on #US extend in the z-direction in portion of #R2 to the left of first vertically extending portion of #US which is adjacent to #R1), the plurality of insulating pillars arranged in the second direction and the third direction (Figure 1, the plurality of #DCHs not on #US are arranged in the second x-direction and the third intersecting y-direction intersecting the z-direction);
a first plate-shaped structure (#US horizontal portion extending through line III-III’, Figure 1, upper isolation region shown to be plate shaped based on Figures 1 and 2A) extending in the first and second directions (Figures 1 and 2A, the identified portion of #US extends in the z and x-directions in the stack) in the first and second stacked bodies to partition the first and second stacked bodies in the third direction (Figure 1, the identified portion of #US partitions the stack at least partially in the y-direction when extending through the first and second identified stack regions);
a second plate-shaped structure (#US vertical portion to the right of line III-III’, Figure 1, upper isolation region shown to be plate shaped based on Figures 1 and 2A) extending in the first and third directions (Figures 1 and 2A, the second identified portion of #US extends in the z and y-directions in the stack) at an end portion of the second stacked body in the second direction away from the first stacked body (Figure 1, let the line III-III’ define an end portion of the second stacked body in the x-direction away from the region #R1); and
a support structure (#DCH at the intersection of the two portions of #US, Figure 1, support structure) extending in the first direction in the second stacked body and disposed where the first plate-shaped structure and the second plate-shaped structure intersect (Figures 1 and 2A, #DCH at the identified intersection extends in the z-direction at least partially in the second stacked body to the right of #R1 where the identified portions of #US intersect).
Regarding Claim 19. Kim discloses The semiconductor memory device according to claim 18, wherein the support structure is a cylindrical column (Figures 1 and 2C, the #DCH at the intersection of the two plate shaped structures of #US is a columnar cylindrical pillar shape) and a diameter of the cylindrical column is greater than a thickness of the first plate-shaped structure in the third direction and is greater than a thickness of the second plate-shaped structure in the second direction (Figure 1, the #DCH at the intersection of the two plate shaped structures of #US has a diameter shown which is greater than a thickness of the horizontal portion of #US contacting it in the y-direction and greater than a thickness of the vertical portion of #US contacting it in the x-direction).
Regarding Claim 20. Kim discloses The semiconductor memory device according to claim 18, further comprising:
a third stacked body adjacent to the end portion of the second stacked body in the second direction (Figure 1, portion of #R2 to the right of the second plate-shaped portion of #US which is adjacent to the portion to the left of the second plate-shaped portion of #US) and including a plurality of conductive layers and a plurality of insulating layers alternately stacked in the first direction (Figures 1 and 2A, the portion of #R2 to the right of the second plate-shaped portion further includes the alternating stack of #120s and #130s); and
a plurality of dummy pillars (Figure 1, array of #DCHs to the right of the second plate-shaped structure) each extending in the first direction in the third stacked body (Figures 1 and 2C, #DCHs not on #US to the right of the second plate shaped portion extend in the z-direction in the portion of #R2 to the right of the third plate-shaped portion), the plurality of dummy pillars arranged in the second direction and the third direction (Figure 1, the plurality of #DCHs to the right of the second plate shaped structure are arranged in the second x-direction and the third intersecting y-direction intersecting the z-direction) and formed with the same material as the insulating pillars ([0052], Figures 1 and 2A, all of the dummy channel support structures are made of insulating material according to [0052]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0315040 A1; Tobioka, Akihiro; 09/2024 – Figure 39 details a plurality of plate structures (#76, dielectric isolation walls) extending in different directions and support pillar structures (#20) located at their intersection points.
US 2024/0055350 A1; Swenson et al.; 02/2024 – Figure 7A details a plurality of plate structures (#166, #164, #120, Figure 7A, dielectric filled slots and isolation regions) extending in different directions and support pillar structures (#146b) located at their intersection points.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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