DETAILED ACTION
This action is responsive to the election received on 08/24/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A and C in the reply filed on 08/24/2026 is acknowledged. Claim(s) 7, 12, and 16-17 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application(s) filed in JAPAN on 03/14/2023 and 02/19/2024. Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/04/2024 and 03/25/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 and 11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6 and 11, the term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as “reasonably close to” or “almost” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how close the thicknesses of the conductive layers (claim 6) or the aperture ratios of the chips (claim 11) need to be in order to be “about equal” or “about the same”, respectively. The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (such as several nanometers or micrometers), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, claim(s) 6 and 11 is/are rejected as being indefinite under 35 U.S.C. 112(b), for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the purposes of this examination, it will be interpreted that any two conductive layers and/or cell chips shown within the same figure scale of the prior art have about equal thicknesses and/or aperture ratios.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-11, and 13-15 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0088551 A1; Kume, Ippei; 03/2023; (“Kume”).
Regarding Claim 1. Kume discloses A semiconductor memory device (Figure 23) comprising:
a substrate (#SB1, Figure 23, semiconductor substrate);
a first cell chip (#50x, Figure 23, cell chip) that is provided on a first direction side of the substrate (Figure 23, #50x is provided on a top z-direction side of #SB1); and
a second cell chip (#40x, Figure 23, cell chip) that is provided between the first cell chip and the substrate (Figure 23, #40x is provided between #50x and #SB1) and is bonded to the first cell chip (Figure 23, #40x is directly bonded to #50x),
wherein the first cell chip (#50x) includes
a first stack (#MS2, Figure 23, stacked body) including a plurality of first memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a first conductive layer (#52, Figure 23, conductor) that is provided on the first direction side of the first stack (Figure 23, #52 is provided on the top z-direction side of #MS2) and is used as a first source line ([0083], #52 is part of the source line),
a second conductive layer (#53, Figure 27, conductor) that is provided on the first direction side of the first conductive layer (Figure 23, #53 is on the top z-direction side of #52) and is electrically connected to the first conductive layer (Figure 23, #53 is directly electrically connected to #52), and
a plurality of first bonding pads (#PD4x, Figure 23, conductors functioning as bonding pads between the chips) that are provided on a first surface of the first cell chip at which the first cell chip is bonded to the second cell chip (Figure 23, #PD4x are provided on a bottom surface of #50x where #40x and #50x are bonded to each other), and
the second cell chip (#40x) includes
a second stack (#MS1, Figure 23, stacked body) including a plurality of second memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a third conductive layer (#41, Figure 23, conductor) that is provided on the first direction side of the second stack (Figure 23, #41 is provided on the top z-direction side of #MS1) and is used as a second source line ([0071], #41 is part of the source line),
a plurality of second bonding pads (#PD3x, Figure 23, conductors functioning as bonding pads between the chips) that are disposed on a second surface of the second cell chip at which the second cell chip is bonded to the first cell chip (Figure 23, #PD3x are provided on a top surface of #40x where #40x and #50x are bonded to each other), and are joined to the plurality of first bonding pads, respectively (Figure 23, #PD3x and #PD4x are respectively bonded to one another), and
a fourth conductive layer (#51x, Figure 23, conductor) that extends in a second direction intersecting the first direction (Figure 23, #51x extends in a y-direction intersecting the z-direction), electrically couples the plurality of second bonding pads (Figure 23, #51x at least partially electrically couples each #PD3x to one another through direct connection to each), and is electrically connected to the third conductive layer (Figure 23, #51x is directly electrically connected to #41), and
wherein the second conductive layer and the fourth conductive layer are electrically connected (Figure 23, #53 and #51x are electrically connected to one another through contact plug CC and the bonding pads).
Regarding Claim 2. Kume discloses The semiconductor memory device according to claim 1,
wherein the second conductive layer (#53) and the fourth conductive layer (#51x) contain conductive materials different from each other ([0084], #53 is made of aluminum; [0150], #51x may contain copper as part of an aluminum/copper alloy formed at the surface of #51x at the interface with #PD3x).
Regarding Claim 3. Kume discloses The semiconductor memory device according to claim 2,
wherein the second conductive layer contains aluminum ([0084], #53 is made of aluminum), and the fourth conductive layer contains copper ([0150], #51x may contain copper as part of an aluminum/copper alloy formed at the surface of #51x at the interface with #PD3x).
Regarding Claim 9. Kume discloses The semiconductor memory device according to claim 1,
wherein the second cell chip further includes a first contact that electrically connects the third conductive layer and the fourth conductive layer (Figure 23, the plurality of vias of #51x may be interpreted as a plurality of integral contacts providing an electrical connection between #41 and #51x).
Regarding Claim 10. Kume discloses The semiconductor memory device according to claim 1,
wherein the first cell chip (#50x) further includes a sixth conductive layer (#CC, Figure 23, contact plug) that extends in the second direction along the first surface (Figure 23, #CC extends in the y-direction “along” a direction parallel to the bottom surface of #50x where “along” does not require direct contact) and electrically couples the plurality of first bonding pads (Figure 23, #CC electrically couples the plurality of bonding pads to one another as part of the overall source line structure), and
the sixth conductive layer is electrically connected to the second conductive layer and the fourth conductive layer (Figure 23, #CC is electrically connected to both #53 and #51x).
Regarding Claim 11. Kume discloses The semiconductor memory device according to claim 1,
wherein an aperture ratio of the second cell chip is about the same as an aperture ratio of the first cell chip (Figure 23, the aperture ratios of #40x and #50x are observed to be about the same).
Regarding Claim 13. Kume discloses A semiconductor memory device (Figure 23) comprising:
a substrate (#SB1, Figure 23, semiconductor substrate);
a first cell chip (#50x, Figure 23, cell chip) that is provided on a first direction side of the substrate (Figure 23, #50x is provided on a top z-direction side of #SB1); and
a second cell chip (#40x, Figure 23, cell chip) that is provided between the first cell chip and the substrate (Figure 23, #40x is provided between #50x and #SB1) and is bonded to the first cell chip (Figure 23, #40x is directly bonded to #50x),
wherein the first cell chip (#50x) includes
a first stack (#MS2, Figure 23, stacked body) including a plurality of first memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a first conductive layer (#52, Figure 23, conductor) that is provided on the first direction side of the first stack (Figure 23, #52 is provided on the top z-direction side of #MS2) and is used as a first source line ([0083], #52 is part of the source line),
a second conductive layer (#53, Figure 27, conductor) that is provided on the first direction side of the first conductive layer (Figure 23, #53 is on the top z-direction side of #52) and is electrically connected to the first conductive layer (Figure 23, #53 is directly electrically connected to #52), and
a plurality of first bonding pads (#PD4x, Figure 23, conductors functioning as bonding pads between the chips) that are provided on a first surface of the first cell chip at which the first cell chip is bonded to the second cell chip (Figure 23, #PD4x are provided on a bottom surface of #50x where #40x and #50x are bonded to each other), and
the second cell chip (#40x) includes
a second stack (#MS1, Figure 23, stacked body) including a plurality of second memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a third conductive layer (#41, Figure 23, conductor) that is provided on the first direction side of the second stack (Figure 23, #41 is provided on the top z-direction side of #MS1) and is used as a second source line ([0071], #41 is part of the source line),
a plurality of second bonding pads (#PD3x, Figure 23, conductors functioning as bonding pads between the chips) that are disposed on a second surface of the second cell chip at which the second cell chip is bonded to the first cell chip (Figure 23, #PD3x are provided on a top surface of #40x where #40x and #50x are bonded to each other), and are joined to the plurality of first bonding pads, respectively (Figure 23, #PD3x and #PD4x are respectively bonded to one another),
a fourth conductive layer (#51x, Figure 23, conductor) that is provided between the plurality of second bonding pads and the third conductive layer (Figure 23, #51x is provided between the PD3x structures and #41) and extends in a second direction intersecting the first direction (Figure 23, #51x extends in a y-direction intersecting the z-direction),
a first contact that electrically connects the third conductive layer and the fourth conductive layer (Figure 23, the plurality of vias of #51x may be interpreted as a plurality of integral contacts providing an electrical connection between #41 and #51x), and
a second contact that electrically connects the plurality of second bonding pads and the fourth conductive layer (Figure 23, [0150], the aluminum/copper alloyed portions of #51x may be interpreted as contacts electrically connecting #PD3x to #51x), and
wherein the second conductive layer and the fourth conductive layer are electrically connected (Figure 23, #53 and #51x are electrically connected to one another through contact plug CC and the bonding pads).
Regarding Claim 14. Kume discloses The semiconductor memory device according to claim 13,
wherein the second conductive layer (#53) and the fourth conductive layer (#51x) contain conductive materials different from each other ([0084], #53 is made of aluminum; [0150], #51x may contain some amount of copper as part of an aluminum/copper alloy in its contact portions formed at the surface of #51x at the interface with #PD3x).
Regarding Claim 15. Kume discloses The semiconductor memory device according claim 14,
wherein the second conductive layer contains aluminum ([0084], #53 is made of aluminum), and
the fourth conductive layer contains copper ([0150], #51x may contain copper as part of an aluminum/copper alloy formed at the surface of #51x at the interface with #PD3x).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0088551 A1; Kume, Ippei; 03/2023; (“Kume”) as applied to claim 1 above, and further in view of US 2024/0155829 A1; Kim et al.; 05/2024; (“Kim”).
Regarding Claim 4. Kume discloses The semiconductor memory device according to claim 1.
Kume does not disclose that the plurality of first bonding pads and the plurality of second bonding pads are disposed in a honeycomb shape when viewed from the first direction.
However, Kim teaches a semiconductor memory device (Figure 4) comprising a plurality of bonding pads (#LP, Figure 4, landing pads) which are arranged in a honeycomb pattern (Figure 4, [0063]) when viewed from a top-down direction.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the first and second bonding pads of Kume in a honeycomb pattern, similar to the landing pads of Kim, since doing so may maximize the number of pads within a given unit area and thus maximize the integration density of the devices (see [0109] of Kim).
Allowable Subject Matter
Claim(s) 5 and 8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches “a first contact that electrically connects the third conductive layer and the fifth conductive layer, and a second contact that electrically connects the fourth conductive layer and the fifth conductive layer”, as recited in claim 5, in combination with all of the other required limitations of the claim.
Regarding Claim 5. Kume discloses The semiconductor memory device according to claim 1,
wherein the second cell chip (#40x) further includes a fifth conductive layer that is provided between the third conductive layer and the fourth conductive layer (Figure 23, the plurality of vias of #51x may be interpreted as another conductive layer between #41 and #51x).
Kume does not disclose a first contact that electrically connects the third conductive layer and the fifth conductive layer, and a second contact that electrically connects the fourth conductive layer and the fifth conductive layer. The fifth conductive layer of Kume is shown to be in direct electrical contact with both the third and fourth conductive layers such that additional contact structures are not necessary to provide claimed electrical connections. Therefore, claim 5 is interpreted to include allowable subject matter and claim 8 is interpreted to include allowable subject matter at least for its dependence on claim 5.
Claim(s) 18-20 is/are allowed. The following is an examiner’s statement of reasons for allowance: None of the cited prior art, either alone or in combination, teaches “a first contact that electrically connects the third conductive layer and the fifth conductive layer, and a second contact that electrically connects the fourth conductive layer and the fifth conductive layer”, as recited in claim 18, in combination with all of the other required limitations of the claim.
Regarding Claim 18. US 2023/0088551 A1; Kume, Ippei; 03/2023; (“Kume”), the closest identified prior art, discloses A semiconductor memory device (Figure 23) comprising:
a substrate (#SB1, Figure 23, semiconductor substrate);
a first cell chip (#50x, Figure 23, cell chip) that is provided on a first direction side of the substrate (Figure 23, #50x is provided on a top z-direction side of #SB1); and
a second cell chip (#40x, Figure 23, cell chip) that is provided between the first cell chip and the substrate (Figure 23, #40x is provided between #50x and #SB1) and is bonded to the first cell chip (Figure 23, #40x is directly bonded to #50x),
wherein the first cell chip (#50x) includes
a first stack (#MS2, Figure 23, stacked body) including a plurality of first memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a first conductive layer (#52, Figure 23, conductor) that is provided on the first direction side of the first stack (Figure 23, #52 is provided on the top z-direction side of #MS2) and is used as a first source line ([0083], #52 is part of the source line),
a second conductive layer (#53, Figure 27, conductor) that is provided on the first direction side of the first conductive layer (Figure 23, #53 is on the top z-direction side of #52) and is electrically connected to the first conductive layer (Figure 23, #53 is directly electrically connected to #52), and
the second cell chip (#40x) includes
a second stack (#MS1, Figure 23, stacked body) including a plurality of second memory cell transistors ([0076] and [0053], stacks comprise a plurality of memory cell transistors),
a third conductive layer (#41, Figure 23, conductor) that is provided on the first direction side of the second stack (Figure 23, #41 is provided on the top z-direction side of #MS1) and is used as a second source line ([0071], #41 is part of the source line),
a plurality of bonding pads (#PD3x, Figure 23, conductors functioning as bonding pads between the chips) that are disposed on a second surface of the second cell chip at that is bonded to the first cell chip (Figure 23, #PD3x are provided on a top surface of #40x where #40x and #50x are bonded to each other), and are joined to the plurality of first bonding pads, respectively (Figure 23, #PD3x and #PD4x are respectively bonded to one another),
a fourth conductive layer (#51x, Figure 23, conductor) that extends in a second direction intersecting the first direction (Figure 23, #51x extends in a y-direction intersecting the z-direction) and electrically couples the plurality of bonding pads (Figure 23, #51x at least partially electrically couples each #PD3x to one another through direct connection to each),
a fifth conductive layer that is provided between the third conductive layer and the fourth conductive layer (Figure 23, the plurality of vias of #51x may be interpreted as another conductive layer between #41 and #51x), and
wherein the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are electrically connected (Figure 23, #53, #41, #51x, and the vias between #51x and #41 are all electrically connected to one another through either direct contact or the contact plug CC and the bonding pads).
Kume does not disclose a first contact that electrically connects the third conductive layer and the fifth conductive layer, and a second contact that electrically connects the fourth conductive layer and the fifth conductive layer. The fifth conductive layer of Kume is shown to be in direct electrical contact with both the third and fourth conductive layers such that additional contact structures are not necessary to provide claimed electrical connections. Therefore, claim 18 is interpreted to be allowable and claims 19-20 are interpreted to be allowable at least for their dependence on claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0284673 A1; Futatsuyama et al.; 08/2024 – Figure 20 discloses a stack of memory arrays on a substrate wherein the respective memory arrays each have a top source line (#126a/b) which are interconnected by a plurality of metal lines and bonding pads at the interface of the stack chips.
US 2023/0397445 A1; Kato, Hisashi; 12/2023 – Figure 4 discloses a stack of memory arrays on a substrate wherein the respective memory arrays each have a top source line (#CSL) which are interconnected by a plurality of metal lines and bonding pads at the interface of the stack chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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