DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Subspecies A, claims 1-3, 5-7, 10-15, and 20 in the reply filed on 8/3/2026 is acknowledged.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the memory cell transistors of claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-15 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 13) As memory cell transistors were neither shown nor described in the specification, it is unclear how to determine if a memory cell transistor is present as claimed.
During examination, “memory cell transistor” was read as “memory cell”.
Claims 14-15 and 20 inherit this rejection for indefiniteness.
(Re Claim 15) “the planes of the…second plate-shaped structures” lacks antecedence, as a second plate-shaped structure was not defined.
During examination, “the planes of the first and second plate-shaped structures” was read as “the plane of the first plate-shaped structure and a plane of a second plate-shaped structure”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi (US 2022/0068858) and Ishihara (US 2021/0225860).
(Re Claim 1) Horiuchi teaches a semiconductor storage device comprising: a first chip (the elements between the first main surface and the second main surface; Fig. 13) that has a first main surface (bottommost surface of 13; Fig. 13) and a second main surface (topmost surface of 13; Fig. 13) and includes memory cells (each interface between the wordlines WL and CL; Fig. 3 and 13); and a second chip (the elements of 2; Fig. 13) that is bonded to the first main surface of the first chip (Fig. 13) and is configured to control operations (“controls the operations of the array region 1; (¶29)) performed on the memory cells of the first chip, wherein the first chip includes:
a stacked body (WL+61 that surround each CL; Fig. 3 and 13) including a plurality of conductive layers (WL; Fig. 3) that are stacked in a first direction (top to bottom; Fig. 13);
a plurality of pillar structures (each CL; Fig. 13) that each include a semiconductor layer (65; Fig. 3)) extending within the stacked body in the first direction;
a pad portion (53c overlapping with P in plan view; Fig. 13) that is exposed at the second main surface (exposed by 12; Fig. 13); and
a connection structure (45+46; Fig. 13) that electrically connects the pad portion and a circuit (the transistors associated with 31 on the right; Fig. 13) provided in the second chip, and includes a first plate-shaped part (left 46+the part of 13 that is between the left 46 and halfway to the right 46; Fig. 13) that extends in the first direction and one of a second direction (the second direction; Fig. 13) and a third direction.
Horiuchi has not been explicitly shown to teach a plurality of partitions that extend within the stacked body in the first direction and a second direction that intersects with the first direction to divide the stacked body in a third direction that intersects with the first direction and the second direction.
Ishihara teaches a first chip (device seen in Fig. 9) including memory cells (each interface between the wordlines WL and CL; Fig. 2 and 9); forming a plurality of partitions (LI-ST; Fig. 6-7 and 9) that extend within a stacked body (WL+22; Fig. 2 and 9) in a first direction (top to bottom; Fig. 9) and a second direction (left to right; Fig. 9) that intersect with the first direction to divide the stacked body in a third direction (into the page as seen in Fig. 9; see Fig. 6 and 7 for reference) that intersects with the first direction and the second direction (Fig. 6-7 and 9).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a plurality of partitions between groupings of pillars structures (Ishihara: each CL; Fig. 6 and 7) and their associated memory cells, as taught by Ishihara, such that the plurality of partitions extends in a direction into the page as seen in Horiuchi’s Fig. 13, to provide a source voltage to Horiuchi’s layer 12. Forming the pillar structures of Horiuchi such that they are grouped as shown in Ishihara’s Fig. 7 allows for close packing (¶55).
(Re Claim 5) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein each of the plurality of partitions includes a first conductive part (Ishihara: 50; Fig. 9) and a first insulation part (Ishihara: 40; Fig. 9) that is provided along a side surface of the first conductive part (the right side surface; Fig. 9), and the first plate-shaped part further includes a second conductive part (the left 46; Fig. 13) and a second insulation part (the part of 13 that is between the left 46 and halfway to the right 46; Fig. 13) that is provided along a side surface (right side surface; Fig. 13) of the second conductive part.
(Re Claim 6) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the first chip further includes an insulation layer (52+54; Fig. 13) provided at the second main surface side and having an opening (P; Fig. 13) through which the pad portion is exposed.
(Re Claim 7) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the first chip further includes an extension portion (53a+53b+remainder of 53c; Fig. 13) extending from the pad portion in a direction parallel to the second main surface, and the connection structure is directly connected to the extension portion (Fig. 13).
(Re Claim 10) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the first chip includes a memory region (to the left of the connection structure; Fig. 13) in which the memory cells are provided and a connection region (everything to the right of the memory region; Fig. 13) adjacent to the memory region in the second direction, and the connection structure extends within an insulation region of the connection region (13 in the connection region; Fig. 13).
(Re Claim 11) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the first chip further includes a connection electrode (rightmost 43; Fig. 13) at the first main surface and connected to the second chip (Fig. 13), and a wiring structure (42+43+44; Fig. 13) connected between the connection structure and the connection electrode, and the pad portion and the circuit provided in the second chip are electrically connected via the connection structure, the wiring structure, and the connection electrode (Fig. 13).
(Re Claim 12) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the stacked body includes the plurality of conductive layers and a plurality of insulation layers (61; Fig. 3) that are alternately stacked in the first direction, and the memory cells are formed at intersections of the pillar structures and the conductive layers functioning as word lines (as defined in claim 1; see also Fig. 3).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi (US 2022/0068858) and Ishihara (US 2021/0225860) as applied to claim 1 above, and further in view of Setta (US 2022/0077090).
(Re Claim 2) Modified Horiuchi teaches the semiconductor storage device according to claim 1, wherein the connection structure further includes a second plate-shaped part (right 46+the part of 13 that is between the left 46 and halfway to the left 46; Fig. 13) that extends in the first direction.
Modified Horiuchi has not been explicitly shown to teach the second plate-shaped part extends in the other one of the second direction and the third direction.
Setta teaches forming a connection structure (each 45 to the left of the leader for 61; Fig. 16) that includes a second plate-shaped structure (right 45 of the connection structure seen in Fig. 16) extending in a third direction (along the left surface of the second plate-shaped structure seen in Fig. 17).
A PHOSITA would find it obvious to form the elements 46 of modified Horiuchi’s connection structure such that they have square cross-sections in a plan view, as taught by Setta, to allow for more material to be used to form the connection structure while maintaining the same lattice spacing for each of Horiuchi’s elements 46 (Horiuchi: ¶¶80-81).
This results in modified Horiuchi teaching the connection structure includes a second plate-shaped structure (left 46+the part of 13 that is between the left 46 and halfway to the right 46; Fig. 13) extending in the third direction (as would be seen in a plan view of modified Horiuchi’s Fig. 13).
(Re Claim 3) Modified Horiuchi teaches the semiconductor storage device according to claim 2, wherein the first plate-shaped part and the second plate-shaped part are spaced apart from each other (Fig. 13).
Claims 13-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi (US 2022/0068858), Ishihara (US 2021/0225860), and Setta (US 2022/0077090).
(Re Claim 13) Horiuchi teaches a semiconductor storage device comprising: a first chip (the elements between the first main surface and the second main surface; Fig. 13) including a plurality of conductive layers (WL surrounding each CL; Fig. 3) and a plurality of insulation layers (61 surrounding each CL; Fig. 3) that are alternately stacked in a first direction (top to bottom; Fig. 13) and a plurality of semiconductor pillars (each CL; Fig. 13) extending through the stacked conductive and insulation layers, wherein memory cell transistors (each interface between the wordlines WL and CL; Fig. 3 and 13; see the 112(b) rejection) are formed at intersections of the semiconductor pillars and a group of the conductive layers (corresponding layers of WL; Fig. 13); and a second chip (the elements of 2; Fig. 13) that is bonded to a first surface of the first chip (bottommost surface of 13; Fig. 13) and is configured to control operations performed on the memory cell transistors of the first chip (“controls the operations of the array region 1; (¶29)), a bonding pad (53c overlapping with P in plan view; Fig. 13) that is exposed at a second surface of the first chip (topmost surface of 13; Fig. 13) that is opposite to the first surface, and a connection structure (45+46; Fig. 13) that electrically connects the bonding pad and a circuit (the transistors associated with 31 on the right; Fig. 13) provided in the second chip.
Horiuchi has not been explicitly shown to teach the first chip further includes a plurality of partitions extending in the first direction and a second direction that intersects with the first direction to divide the stacked conductive and insulation layers in a third direction that intersects with the first direction and the second direction; and
the connection structure includes a first plate-shaped structure having a plane that is parallel to the third direction.
Ishihara teaches a first chip (device seen in Fig. 9) including memory cells (each interface between the wordlines WL and CL; Fig. 2 and 9); forming a plurality of partitions (LI-ST; Fig. 6-7 and 9) that divide stacked conductive (WL; Fig. 2 and 9) and insulation layers (22; Fig. 2 and 9) in a third direction direction (into the page as seen in Fig. 9) that intersects with a first direction (top to bottom; Fig. 9) and a second direction (left to right; Fig. 9), wherein the first direction intersects the second direction.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a plurality of partitions between groupings of pillars structures (Ishihara: each CL; Fig. 6 and 7) and their associated memory cells, as taught by Ishihara, such that the plurality of partitions extends in a direction into the page as seen in Horiuchi’s Fig. 13, to provide a source voltage to Horiuchi’s layer 12. Forming the pillar structures of Horiuchi such that they are grouped as shown in Ishihara’s Fig. 7 allows for close packing (¶55).
The first direction, second direction, and third direction are respectively then top to bottom, left to right, and into the page; as seen in Horiuchi’s Fig. 13.
Setta teaches forming a connection structure (each 45 to the left of the leader for 61; Fig. 16) that includes a first plate-shaped structure (left 45 of the connection structure seen in Fig. 16) having a plane that is parallel to the third direction (left surface of the first plate-shaped structure seen in Fig. 17).
A PHOSITA would find it obvious to form the elements 46 of modified Horiuchi’s connection structure such that they have square cross-sections in a plan view, as taught by Setta, to allow for more material to be used to form the connection structure while maintaining the same lattice spacing for each of Horiuchi’s elements 46 (Horiuchi: ¶¶80-81).
This results in modified Horiuchi teaching the connection structure includes a first plate-shaped structure (left 46+the part of 13 that is between the left 46 and halfway to the right 46; Fig. 13) having a plane (the left side surface as seen in Horiuchi’s Fig. 13) that is parallel to the third direction (compare Setta’s Fig. 17 and Horiuchi’s Fig. 13).
(Re Claim 14) Modified Horiuchi teaches the semiconductor storage device according to claim 13, wherein the connection structure further includes a second plate-shaped structure (right 46+the part of 13 that is between the left 46 and halfway to the left 46; Fig. 13) having a plane (the right side surface as seen in Horiuchi’s Fig. 13) that is parallel to the third direction (compare Setta’s Fig. 17 and Horiuchi’s Fig. 13).
(Re Claim 15) Modified Horiuchi teaches the semiconductor storage device according to claim 13, wherein the planes of the first and second plate-shaped structures (right 46+the part of 13 that is between the left 46 and halfway to the left 46; Fig. 13) are orthogonal to each other (where the plane of the second plate-shape structure is the top surface as would be seen in a plan view of modified Horiuchi’s Fig. 13; compare Setta’s Fig. 17 and Horiuchi’s Fig. 13).
(Re Claim 20) Modified Horiuchi teaches the semiconductor storage device according to claim 13, wherein the connection structure is connected to the bonding pad through a conductive wiring (53a+53b+remainder of 53c; Fig. 13) that extends from the bonding pad parallel to the first surface and is in contact with the connection structure (Fig. 13).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oda et al. (US 2021/0375790) teaches forming connection structures in an array pattern (Fig. 3B).
Tomimatsu et al. (US 2022/0084970) teaches forming a bonding pod (Fig. 9B).
Watanabe et al. (US 2022/0077089) teaches forming a bonding pad (Fig. 1).
Wada (US 2022/0270992) teaches forming a bonding pad (Fig. 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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