DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 and Modification B in the reply filed on 01 July 2026 is acknowledged. Claims 10-18 are withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Minhee Cho et al. (US 20230009575 A1; hereinafter Cho).
Regarding Claim 1, Cho discloses a semiconductor device (Fig. 2) comprising:
a substrate (101; ¶0028);
a first electrode layer (104; ¶0028) disposed over the substrate (101);
an interlayer insulating layer (106; ¶0036) having an opening (108; ¶0036) that exposes the first electrode layer (104);
an oxide semiconductor layer (135; ¶0028, ¶0042, ¶0046) formed along a surface (sides and bottom) of the opening (108) and connected to the first electrode layer (104);
a gate insulating layer (144a/144b; ¶0040/¶0046) formed along a surface (internal surfaces) of the oxide semiconductor layer (135);
a stacked structure including a first gate electrode layer (146; ¶0028), a first insulating layer (148; ¶0037), a second gate electrode layer (150; ¶0028), and a second insulating layer (152; ¶0050) stacked in a vertical direction (Z) while filling a remaining space of the opening (108) in which the oxide semiconductor layer (135) and the gate insulating layer (144a/144b) are formed; and
a second electrode layer (192; ¶0054) disposed over the stacked structure and the oxide semiconductor layer (144a/144b) and connected to the oxide semiconductor layer (135) (they are electrically connected).
Cho does not expressly disclose wherein the second insulating layer (gate cap 152) is an insulating material. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the gate cap layer (152) made of an insulating material to prevent electrical shorts while protecting the second gate electrode.
Regarding Claim 5, modified Cho teaches the semiconductor device according to claim 1, wherein, according to a second voltage applied to the second gate electrode (150) layer, a current flow is generated through the oxide semiconductor layer (135) between the first electrode layer (104) and the second electrode layer (192) (these limitations are drawn to the manner of operation of the device, and are implicitly satisfied by meeting the structural limitations of the claims).
Regarding Claim 6, modified Cho teaches the semiconductor device according to claim 5, wherein the second voltage is applied to the second gate electrode layer (150) in a turn-on period of a transistor (these limitations are drawn to the manner of operation of the device, and are implicitly satisfied by meeting the structural limitations of the claims).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of the non-patent literature (of record) “Extremely high-gain source-gate transistors” by Jiawei Zhang et al. year: 2019; hereinafter Zhang.
Regarding Claim 2, Cho teaches the semiconductor device according to claim 1, wherein the first electrode layer (104) and the oxide semiconductor layer (135) are in direct contact with each other (as shown in Fig. 2).
Cho does not expressly disclose wherein the direct contact between the metal electrode layer (104) and oxide semiconductor channel (135) form a Schottky barrier, and wherein the first gate electrode layer functions to reduce the Schottky barrier (wherein this is functional language directed toward the intended use of the device, and therefore satisfied by meeting the structural limitations of the claim proceeding below).
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the direct contact between the metal electrode comprising the same materials as the instant invention (104; ¶0032) to the oxide semiconductor comprising the same materials as the instant invention (144a/144b; ¶0042) would form a Schottky barrier.
Furthermore, the recitation of “wherein the first gate electrode layer functions to reduce the Schottky barrier” is functional language describes the operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2144 II.
Alternatively, in the same field of endeavor, Zhang discloses (see pages 1-2) utilizing a Schottky barrier between the semiconductor channel (equivalent to Cho’s 135) and the source electrode (equivalent to Cho’s 104). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have this Schottky interface (of Zhang) in the device of Cho in order to provide the resulting advantages including high intrinsic gain, low-voltage saturation, insensitivity to channel length, and improved stability (Zhang; page 1).
Regarding Claim 3, modified Cho teaches the semiconductor device according to claim 2, wherein, according to a first voltage applied to the first gate electrode layer (146), conductive carriers are accumulated in an area of the oxide semiconductor layer (135), which is adjacent to the first gate electrode layer (146) (these limitations are implicitly satisfied as they are directed toward the manner of operation of the device, and the oxide semiconductor channel layer 135 is adjacent the first gate electrode layer 146).
Regarding Claim 4, modified Cho teaches the semiconductor device according to claim 3, wherein the first voltage is applied to the first gate electrode layer (146) during a turn-on period and a turn-off period of a transistor (these limitations are drawn to the manner of operation of the device, and are implicitly satisfied by meeting the structural limitations of the claims).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Masaya Toda et al. (US 20240321995 A1; hereinafter Toda).
Regarding Claim 8, modified Cho teaches the semiconductor device according to claim 1, but does not expressly disclose wherein the stacked structure has a width that decreases from top to bottom.
In the same field of endeavor, Toda teaches a similar device (Fig. 9 and Fig. 10) that shows a stacked structure (16) that has a shape that is straight (Fig. 9) or tapered with a width that decreases from top to bottom (Fig. 10).
It has been held that is not inventive by change the shape in view of In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the shape of the stacked structure of Toda for the device of Cho in order to realize a transistor with excellent characteristics (Toda; ¶0164).
Regarding Claim 9, modified Cho teaches the semiconductor device according to claim 1, but does not expressly disclose further comprising: a memory element electrically connected to the first electrode layer between the first electrode layer and the substrate.
In the same field of endeavor, Toda teaches a similar device (Fig. 12) with a transistor (TR; ¶0169) with a top (14; ¶0031) and bottom (12; ¶0031) electrode, and a capacitor (CA) connected to the bottom electrode (12) and located between the bottom electrode and the substrate (10; ¶0175).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the configuration of Toda in the device of Cho in order to provide a memory device with excellent charge storage characteristics (Toda; ¶0183).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 7, the prior art of record teaches the limitations of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein the first electrode layer has an island shape, wherein a plurality of first electrode layers are arranged along a first direction parallel to an upper surface of the substrate and a second direction, the second direction being parallel to the upper surface of the substrate and intersecting the first direction, wherein the stacked structure extends in the second direction to overlap the plurality of first electrode layers arranged in the second direction, and wherein the second electrode layer extends in the first direction to overlap the plurality of first electrode layers arranged in the first direction. This is most clearly shown in Fig. 5A.
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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