DETAILED ACTION
This action is responsive to the election received on 08/03/2026
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-9 and 16-18) in the reply filed on 08/03/2026 is acknowledged.
Claim(s) 10-15 and 19-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in EP on 03/08/2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/05/2024 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 3, 4-5, 9, and 16-17 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 3, line 2, “between the dielectric spacers and the further dielectric layer” in order to agree with previous recitations of dielectric spacers (plural) since there has been no previous recitation of a singular dielectric spacer;
Claims 4 and 16, line 3, “the layer stack comprising at least” deleting a duplicated phrase;
Claims 9 and 17, line 3, “at least one of the dielectric spacers and the further dielectric layer” since there has been no previous recitation of a dielectric layer but there has been a recitation of dielectric spacers.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the polycrystalline silicon layer extends laterally further from the window than does the further dielectric layer" in lines 3-4 of the claim and claim 9 recites the limitation “at least one of the dielectric spacers and the further dielectric layer comprise a silicon nitride material” in lines 3-4 of the claim. There is insufficient antecedent basis for this limitation in the claims. Both of these claims depend on claim 1 and have not recited “a further dielectric layer”. However, “a further dielectric layer” has been recited in the second line of claim 2. It is therefore unclear if claims 8 and 9 should depend on claim 2 or if each of these recitations should refer to “a further dielectric layer” as a new element. Therefore, claims 8 and 9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, both instances of “the further dielectric layer” in claims 8 and 9 will be interpreted to read as “a further dielectric layer” as a new element not previously recited.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2010/0127352 A1; El-Diwany et al.; 05/2010; (“El-Diwany”).
Regarding Claim 1. El-Diwany discloses A SiGe Heterojunction Bipolar Transistor, HBT (Figure 5I, Bipolar Junction Transistor including an SiGe heterojunction according to [0025], examiner notes that some element numbers identified below are present as part of the method of making Figures 5A-5I but not explicitly recited in the final figure), comprising an emitter (MONO portion of #516, Figures 5I, emitter plug), a base (#506, Figure 5I, base epitaxial material) and a collector (#504, Figure 5I, semiconductor material which functions as a collector based on [0040]), wherein:
the collector comprises an n-doped implanted region (abstract and [0011], collector is n-type doped);
the base comprises a p-doped SiGe layer ([0025], base is an SiGe layer which is p-type doped according to [0036]), within a layer stack comprising at least the p-doped SiGe layer and having an upper surface (Figure 5I, #506 is part of a layer stack comprising the p-type SiGe layer having an upper surface), the layer stack being over and in direct contact with the collector (Figure 5I, #506 is over and in direct contact with #504);
the emitter comprises an n-doped monocrystalline silicon emitter (Figure 5I, lower portion of #516 is monocrystalline silicon which is N-type doped according to [0027] to form the NPN structure) over and in direct contact with a first area of the upper surface of the layer stack (Figure 5I, MONO portion of #516 is in direct contact with a first area of #506);
wherein the HBT further comprises:
an epitaxial silicon layer (#522, Figure 5I, monocrystalline silicon layer epitaxially grown according to [0036]) over and in direct contact with a second area of the upper surface of the layer stack (Figure 5I, #522s are over and in direct contact with a second area of the top surface of #506), and for providing an electrical connection to the base (Figure 5I, #522s are directly electrically connected to #506);
a polycrystalline silicon layer (POLY portion of #516, Figure 5I) for providing an electrical connection to the emitter (Figure 5I, POLY is directly electrically connected to MONO);
an oxide layer (#510, Figure 5I, thin oxide layer) over and in direct contact with a third area of the upper surface of the layer stack (Figure 5I, #510 is over and in direct contact with an area of #506) between the first area and the second area (Figure 5I, the contact interface between #506 and #510 is between the contact interfaces of #506 with MONO and #522s respectively), wherein the oxide layer and the n-doped monocrystalline silicon emitter are within a window in the epitaxial silicon layer (Figure 5I, MONO and #510 are within a window defined by the sidewalls of #522), wherein the window has sidewalls (Figure 5I, interior sidewalls of #522);
dielectric spacers (#526, Figure 5I, nitride spacers) on the sidewalls of the window and over the oxide layer (Figure 5I, #526s are on the sidewalls of #522 and over #510), and providing electrical isolation between the epitaxial silicon layer and the polycrystalline silicon layer (Figure 5I, #526 provides electrical isolation between #522 and POLY); and
wherein the epitaxial silicon layer extends beneath the dielectric spacers on the sidewalls of the window (Figure 5I, #522s extend beneath #526 on the sidewalls of the window).
Regarding Claim 2. El-Diwany discloses The SiGe HBT according to claim 1, further comprising
a further dielectric layer (#530, Figure 5I, dielectric material), over the epitaxial silicon layer (Figure 5I, #530 is over #522) and forming an upper part of the sidewalls of the window (Figure 5I, interior sidewalls of #530 facing #532 may be interpreted as an upper part of the window sidewalls), and separated from an upper part of the dielectric spacers by a further oxide layer (#514, Figure 5I, left/right portions of #530 are at least partially separated from opposing right/left upper portions of #526 by top oxide layer #514).
Regarding Claim 3. El-Diwany discloses The SiGe HBT according to claim 2, wherein
the epitaxial silicon layer extends upwardly to fill a gap, below the further oxide layer (Figure 5I, #522s extend upwardly to fill a gap which is below #514s where below is interpreted to mean at a lower vertical level and not required to overlap), between the dielectric spacers and the further dielectric layer (Figure 5I, #522s at least partially fill a gap between lower portion of #530 and lower portions of #526).
Regarding Claim 7. El-Diwany discloses The SiGe HBT according to claim 1, wherein
the HBT is free from any voids between the oxide layer and the epitaxial silicon layer (Figure 5I, no voids are present between #510 and #522).
Regarding Claim 8. El-Diwany discloses The SiGe HBT according to claim 1, wherein
the polycrystalline silicon layer extends laterally further from the window than does [[the]] a further dielectric layer (#514, Figure 5I, #POLY extends laterally further from both the sidewalls and the center of the window than thick oxide layer #514).
Regarding Claim 9. El-Diwany discloses The SiGe HBT according to claim 1, wherein
at least one of the dielectric spacers and [[the]] a further dielectric layer comprise a silicon nitride material ([0037], #526 is a silicon nitride spacer).
Regarding Claim 17. El-Diwany discloses The SiGe HBT according to claim 2, wherein
at least one of the dielectric spacers and the further dielectric layer comprise a silicon nitride material ([0037], #526 is a silicon nitride spacer).
Regarding Claim 18. El-Diwany discloses The SiGe HBT according to claim 1, wherein
the HBT is free from any voids between the oxide layer and the epitaxial silicon layer (Figure 5I, no voids are present between #510 and #522).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0127352 A1; El-Diwany et al.; 05/2010; (“El-Diwany”) as applied to claims 1 and 2 above, and further in view of US 7,777,255 B2; Rucker et al.; 08/2010; (“Rucker”).
Regarding Claim 4. El-Diwany discloses The SiGe HBT according to claim 1.
El-Diwany does not disclose that the layer stack comprising at least the p-doped SiGe layer further comprises a silicon layer over the SiGe layer, wherein the silicon layer over the SiGe layer is p-doped for providing an electrical connection between the base and the epitaxial silicon layer.
However, Rucker teaches a bipolar heterojunction transistor (Figure 3) wherein the base layer stack (#4, Figure 3, first epitaxial base layer) comprising a p-doped SiGe layer (#4, column 8, lines 16-19, middle layer may be SiGe and the entire layer is p-doped) further comprises a silicon layer over the SiGe layer (column 8, lines 16-19, top layer may be Si) wherein the silicon layer is p-doped (column 8, lines 16-19, the entire layer is p-doped) for providing an electrical connection between the base and an epitaxial silicon layer (Figure 3, the p-doped top silicon layer of #4 serves to form an electrical connection between the underlying SiGe layer and the overlying #12 which includes an epitaxial p-type silicon layer according to column 8, lines 42-62).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the upper p-doped silicon layer over the SiGe layer from Rucker in the device of El-Diwany since that appropriately p-doped Si layer reduces the base resistance at the outer portion of the base and avoids increased base-collector capacitances (see column 4 line 59 through column 5 line 5).
Regarding Claim 5. El-Diwany in view of Rucker discloses The SiGe HBT according to claim 4, wherein
a doping level of the silicon layer over the SiGe layer is uniform and in a range 1E19 to 1E21 cm-3 (Rucker, column 4 line 59 through column 5 line 5, the doping concentration may be greater than 2E19 and less than 2E20 cm-3 and interpreted to be uniform or homogenous based on column 8 lines 63-64 which presents non-homogenous doping as an optional alternative).
Regarding Claim 6. El-Diwany discloses The SiGe HBT according to claim 1.
El-Diwany does not disclose that a doping level of the epitaxial silicon layer is uniform and in a range of 1E19-1E21 cm-3.
However, Rucker teaches a bipolar heterojunction transistor (Figure 3) wherein the base layer stack (#4, Figure 3, first epitaxial base layer) comprising a p-doped SiGe layer (#4, column 8, lines 16-19, middle layer may be SiGe and the entire layer is p-doped) underneath a p-type epitaxial silicon contact layer (#12, Figure 3, raised base connection layer which includes an epitaxial p-type silicon layer according to column 8, lines 42-62) wherein a doping level of the epitaxial silicon layer is uniform and in a range of 1E19-1E21 cm-3 (column 4 line 59 through column 5 line 5, the doping concentration may be greater than 2E19 and less than 2E20 cm-3 and interpreted to be uniform or homogenous based on column 8 lines 63-64 which presents non-homogenous doping as an optional alternative).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the appropriately doped epitaxial p-doped silicon layer over the SiGe layer from Rucker in the device of El-Diwany since that appropriately p-doped Si layer reduces the base resistance at the outer portion of the base and avoids increased base-collector capacitances (see column 4 line 59 through column 5 line 5).
Regarding Claim 16. El-Diwany discloses The SiGe HBT according to claim 2.
El-Diwany does not disclose that the layer stack comprising at least the p-doped SiGe layer further comprises a silicon layer over the SiGe layer, wherein the silicon layer over the SiGe layer is p-doped for providing an electrical connection between the base and the epitaxial silicon layer.
However, Rucker teaches a bipolar heterojunction transistor (Figure 3) wherein the base layer stack (#4, Figure 3, first epitaxial base layer) comprising a p-doped SiGe layer (#4, column 8, lines 16-19, middle layer may be SiGe and the entire layer is p-doped) further comprises a silicon layer over the SiGe layer (column 8, lines 16-19, top layer may be Si) wherein the silicon layer is p-doped (column 8, lines 16-19, the entire layer is p-doped) for providing an electrical connection between the base and an epitaxial silicon layer (Figure 3, the p-doped top silicon layer of #4 serves to form an electrical connection between the underlying SiGe layer and the overlying #12 which includes an epitaxial p-type silicon layer according to column 8, lines 42-62).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the upper p-doped silicon layer over the SiGe layer from Rucker in the device of El-Diwany since that appropriately p-doped Si layer reduces the base resistance at the outer portion of the base and avoids increased base-collector capacitances (see column 4 line 59 through column 5 line 5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2009/0321879 A1; John et al,; 12/2009 – Figure 11 discloses an HBT including an epitaxial doped silicon layer (#163) in contact with an upper surface of a layer stack (#150) including an SiGe base layer (#161) and extending underneath a dielectric spacer (#142).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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