Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 objected to because of the following informalities: the claim begins “wherein an arc path diode connected,” however it would more naturally be read and for the purpose of compact prosecution it will be interpreted as “wherein an arc path diode is connected”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak et al. (US20200373321A1, hereinafter Kwak).
Regarding claim 1, Kwak discloses a semiconductor device comprising:
a semiconductor substrate having a first surface including a memory cell area (Fig. 5 substrate 10 has memory block cell array 110 disposed on it);
a first chipping detection circuit on the first surface of the semiconductor substrate and surrounding the memory cell area (Fig. 5 logic structure P on surface of substrate 10 comprising bottom wiring lines 23A/23B/23C and is on the peripheral and so it surrounds memory cell array 110); and
a chip guard on the first surface of the semiconductor substrate (Fig. 5 the combination of discharge plate 30, discharge path DP, and discharge transistor TRSD constitute a chip guard and are disposed on substrate 10), wherein
a portion of the chip guard overlaps the first chipping detection circuit in a direction perpendicular to the first surface of the semiconductor substrate (Fig. 5 a portion of discharge path DP overlaps source plate 11).
Regarding claim 2, Kwak discloses the semiconductor device of claim 1,
wherein the first chipping detection circuit includes a lower structure separated into a plurality of portions and an upper structure connecting the plurality of portions of the lower structure to each other (Fig. 5 see plurality of bottom wiring lines 23B that are connected to one another by bottom wiring lines 23C).
Regarding claim 3, Kwak discloses the semiconductor device of claim 2,
wherein a plurality of portions in the chip guard are separated from each other and connected to each other by a chip guard connection line (Fig. 5 discharge path DP has plurality of wiring portions and connected to each other with a line straight down to substrate 10).
Regarding claim 7, Kwak discloses the semiconductor device of claim 3,
wherein the chip guard includes a chip guard doped area near the first surface of the semiconductor substrate (Fig. 5 discharge path DP is connected to source S of discharge transistor TRSD), a chip guard wire on the chip guard doped area (Fig. 5 discharge path has bottom wiring layer 23A disposed on source S of discharge transistor TRSD), and a chip guard via connecting the chip guard doped area and the chip guard wire (Fig. 5 see wire directly connecting source S of discharge transistor TRSD to bottom wiring layer 23A within discharge path DP).
Regarding claim 9, Kwak discloses the semiconductor device of claim 3,
wherein the chip guard connection line bypasses the lower structure of the first chipping detection circuit to connect the plurality of portions of the chip guard (Fig. 5 discharge path DP directly connects discharge plate 30 to substrate 10 bypassing the peripheral circuit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (US20200373321A1).
Regarding claim 4, Kwak teaches the semiconductor device of claim 3,
wherein the plurality of portions of the chip guard overlap the upper structure of the first chipping detection circuit in a vertical direction (While Kwak does not explicitly disclose the plurality of portions of the discharge path DP overlapping the peripheral bottom wiring lines 23A/23B/23C, the primary function of the discharge path is to provide a discharge path from the discharge plate to the substrate. A rearrangement of discharge path to be vertically overlapping with the peripheral circuit would not provide any new or unexpected results as the primary function of providing a discharge path from the discharge plate to the substrate is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the discharge path to vertically overlap the peripheral circuit, see MPEP 2144.04(VI)(B)).
Regarding claim 8, Kwak teaches the semiconductor device of claim 7,
wherein the chip guard doped area is doped with P-type impurities (While Kwak does not explicitly teach the doping of the source region of discharge transistor TRSD, as there are a finite number of identified, predictable solutions, specifically either N or P doped, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try doping the source with P-type impurities).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (US20200373321A1) in view of Nam (US20220216197A1).
Regarding claim 5, Kwak teaches the semiconductor device of claim 4.
Kwak does not appear to teach
wherein an arc path diode connected between the lower structure of the first chipping detection circuit and the semiconductor substrate.
Nam teaches
wherein an arc path diode connected between the lower structure of the first chipping detection circuit and the semiconductor substrate (Par. 14 “The discharge structure PS may include a first diode D1, a first discharge contact plug 106′, a second discharge contact plug 108”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kwak with the teachings of Nam because as both Kwak and Nam teach suitable discharge structures, it would have been obvious to substitute Kwak’s discharge transistor to the substrate with a Nam’s discharge diode to the substrate to achieve the predictable result of forming a discharge diode to the substrate.
Regarding claim 6, the combination of Kwak and Nam teaches the semiconductor device of claim 5,
wherein the arc path diode includes an N-type doped area and a P-type doped area in the semiconductor substrate, which are near the first surface of the semiconductor substrate (Nam fig. 1 par. 36 “[t]he first diode D1 may be defined by a junction region 104′ and the substrate 101.” As Nam teaches the use of a discharge diode, they also teach the specific structure of a discharge diode).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kwak (US20200373321A1) in view of Park (US20090091001A1).
Regarding claim 14, Kwak teaches the semiconductor device of claim 1.
Kwak does not appear to teach
a chip dam on the first surface of the semiconductor substrate, wherein the chip dam surrounds the first chipping detection circuit and the chip guard.
Park teaches
a chip dam on the first surface of the semiconductor substrate, wherein the chip dam surrounds the first chipping detection circuit and the chip guard (Par. 43 “The crack-propagation preventing unit 270 formed nearby an outer edge of the semiconductor chip functions as a dam for preventing the defect such as a crack or partial chipping, which may occur around the edge part of the semiconductor chip in the wafer level semiconductor package”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kwak with the teachings of Park because the introduction of a peripheral dam “prevent[s] the defect such as a crack or partial chipping” (Park par. 43).
Allowable Subject Matter
Claims 10-13 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10 and its dependent claims. The closest prior art (US20200373321A1, US20220216197A1, US20090091001A1) teaches the semiconductor device of claim 2, wherein
the lower structure of the first chipping detection circuit includes a chipping detection circuit gate on the semiconductor substrate, a plurality of chipping detection circuit wires on the chipping detection circuit gate (Kwak fig. 5 lower wiring layer 23A connected to transistor TRXDEC which has gate G on substrate 10 and connects to plurality of lower wiring layer 23B/23C)
However, the closest prior art does not teach in combination with the other claimed elements
a plurality of chipping detection circuit vias; and
the plurality of chipping detection circuit vias connect the chipping detection circuit gate and the plurality of chipping detection circuit wires.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Regarding claim 15, the closest prior art (US20200373321A1, US20220216197A1, US20090091001A1) teaches the semiconductor device of claim 14, further comprising
a second chipping detection circuit on the first surface of the semiconductor substrate (While Kwak does not explicitly disclose a second chipping detection circuit, the primary function of Kwak’s lowing wiring layers 23A/23B/23C is to provide connections for the peripheral circuit. A duplication of a lower wiring layers 23A/23B/23C to form a second chipping detection circuit would not provide any new or unexpected results as the primary function of providing connections for the peripheral circuit is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate lowing wiring layers 23A/23B/23C to form a second chipping detection circuit on the first surface of the semiconductor substrate, see MPEP 2144.04(VI)(B)).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the second chipping detection circuit is between the first chipping detection circuit and the chip guard and between the first chipping detection circuit and the chip dam.
Regarding claim 16 and its dependent claims. The closest prior art (US20200373321A1, US20220216197A1, US20090091001A1) teaches a semiconductor device comprising:
a semiconductor substrate having a first surface including a memory cell area (Kwak fig. 5 substrate 10 has memory block cell array 110 disposed on it);
a first chipping detection circuit on the first surface of the semiconductor substrate and surrounding the memory cell area (Kwak fig. 5 logic structure P on surface of substrate 10 comprising bottom wiring lines 23A/23B/23C and is on the peripheral and so it surrounds memory cell array 110);
a chip guard on the first surface of the semiconductor substrate and around the memory cell area (Kwak fig. 5 the combination of discharge plate 30, discharge path DP, and discharge transistor TRSD constitute a chip guard and are disposed on substrate 10);
a chip dam on the first surface of the semiconductor substrate, the chip dam surrounding the first chipping detection circuit and the chip guard (Park par. 43 “The crack-propagation preventing unit 270 formed nearby an outer edge of the semiconductor chip functions as a dam for preventing the defect such as a crack or partial chipping, which may occur around the edge part of the semiconductor chip in the wafer level semiconductor package”); and
a second chipping detection circuit on the first surface of the semiconductor substrate (While Kwak does not explicitly disclose a second chipping detection circuit, the primary function of Kwak’s lowing wiring layers 23A/23B/23C is to provide connections for the peripheral circuit. A duplication of a lower wiring layers 23A/23B/23C to form a second chipping detection circuit would not provide any new or unexpected results as the primary function of providing connections for the peripheral circuit is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate lowing wiring layers 23A/23B/23C to form a second chipping detection circuit on the first surface of the semiconductor substrate, see MPEP 2144.04(VI)(B)),
the first chipping detection circuit includes a lower structure separated into a plurality of portions and an upper structure connecting the plurality of portions of the lower structure to each other (Kwak fig. 5 see plurality of bottom wiring lines 23B that are connected to one another by bottom wiring lines 23C),
the chip guard has a plurality of portions separated from each other,
the plurality of portions of the chip guard are alternately disposed with the lower structure of the first chipping detection circuit (Kwak fig. 5 discharge path DP has plurality of wiring portions and connected to and separate from each other with a line straight down to substrate 10), and
the plurality of portions of the chip guard overlap the upper structure of the first chipping detection circuit in a direction perpendicular to the first surface (While Kwak does not explicitly disclose the plurality of portions of the discharge path DP overlapping the peripheral bottom wiring lines 23A/23B/23C, the primary function of the discharge path is to provide a discharge path from the discharge plate to the substrate. A rearrangement of discharge path to be vertically overlapping with the peripheral circuit would not provide any new or unexpected results as the primary function of providing a discharge path from the discharge plate to the substrate is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the discharge path to vertically overlap the peripheral circuit, see MPEP 2144.04(VI)(B)).
However, the closest prior art does not teach in combination with the other claimed elements
the second chipping detection circuit is between the first chipping detection circuit and the chip guard and between the first chipping detection circuit and the chip dam.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Regarding claim 19 and its dependent claim. The closest prior art (US20200373321A1, US20220216197A1) teaches a semiconductor device comprising:
a first semiconductor substrate including a memory cell driving circuit (Kwak fig. 5 substrate 10 logic structure disposed on it);
a second semiconductor substrate bonded to the first semiconductor substrate and including a memory cell area (Kwak fig. 5 substrate 10 has memory block cell array 110 disposed on it);
a first chipping detection circuit between the first semiconductor substrate and the second semiconductor substrate and surrounding the memory cell area (Kwak fig. 5 logic structure P on surface of substrate 10 comprising bottom wiring lines 23A/23B/23C and is on the peripheral and so it surrounds memory cell array 110);
a chip guard between the first semiconductor substrate and the second semiconductor substrate (Kwak fig. 5 the combination of discharge plate 30, discharge path DP, and discharge transistor TRSD constitute a chip guard and are disposed on substrate 10), a portion of the chip guard overlapping the first chipping detection circuit in a direction perpendicular to the first semiconductor substrate and the second semiconductor substrate (While Kwak does not explicitly disclose the plurality of portions of the discharge path DP overlapping the peripheral bottom wiring lines 23A/23B/23C, the primary function of the discharge path is to provide a discharge path from the discharge plate to the substrate. A rearrangement of discharge path to be vertically overlapping with the peripheral circuit would not provide any new or unexpected results as the primary function of providing a discharge path from the discharge plate to the substrate is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the discharge path to vertically overlap the peripheral circuit, see MPEP 2144.04(VI)(B)); and
an arc path diode connected between the first chipping detection circuit and the first semiconductor substrate (Nam par. 14 “The discharge structure PS may include a first diode D1, a first discharge contact plug 106′, a second discharge contact plug 108”), wherein
the first chipping detection circuit includes a lower structure separated into a plurality of portions and an upper structure connecting the plurality of portions of the lower structure to each other (Fig. 5 see plurality of bottom wiring lines 23B that are connected to one another by bottom wiring lines 23C),
the lower structure of the first chipping detection circuit includes a chipping detection circuit gate on the first semiconductor substrate, a plurality of chipping detection circuit wires on the chipping detection circuit gate (Kwak fig. 5 lower wiring layer 23A connected to transistor TRXDEC which has gate G on substrate 10 and connects to plurality of lower wiring layer 23B/23C),
the upper structure of the first chipping detection circuit includes a chipping detection circuit connection wire and a chipping detection circuit connection via (Kwak fig. 5 lower wiring layers 23A/23B are connected by bottom contact plugs 24),
the chipping detection circuit connection wire spans between at least two of the plurality of portions of the lower structure (Kwak fig. 5 bottom contact plug 24 spans at least two of the plurality of portions of the lower wiring layers),
the chip guard includes a chip guard doped area near the first surface of the first semiconductor substrate (Kwak fig. 5 discharge path DP is connected to source S of discharge transistor TRSD), a chip guard wire on the chip guard doped area (Kwak fig. 5 discharge path has bottom wiring layer 23A disposed on source S of discharge transistor TRSD), and a chip guard via connecting the chip guard doped area and the chip guard wire (Kwak fig. 5 see wire directly connecting source S of discharge transistor TRSD to bottom wiring layer 23A within discharge path DP).
However, the closest prior art does not teach in combination with the other claimed elements
a plurality of chipping detection circuit vias connecting the chipping detection circuit gate and the plurality of chipping detection circuit wires, and
the chipping detection circuit connection via connects the lower structure and the chipping detection circuit connection wire.
Additionally, the closest prior art does not teach the above in combination with the further limitations of the dependent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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