DETAILED ACTION
This office action is in response to Application No.18/595,698, filed on 5 March 2024. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-13, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by Taatizadeh (“Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation”) or, in the alternative, under 35 U.S.C. 103 as obvious over Taatizadeh in view of Mahmud (US 2023/0004701).
Regarding claim 1, Taatizadeh discloses a method for dynamically refining hardware assertion checkers of an integrated circuit (IC) design, the method comprising: receiving a plurality of hardware assertion checkers (p. 2120, §B, ¶1); receiving one or more design constraints (p. 2122, col. 1, ¶1); based at least in part on applying a cost prediction model to the plurality of hardware assertion checkers, generating a predicted overhead cost associated with the plurality of hardware assertion checkers (p. 2121, Fig. 2, col. 1; p. 2121, §C); based at least in part on the predicted overhead cost and the one or more design constraints, selecting an optimal hardware assertion checker set (p. 2120, Fig. 1; p. 2124, col. 1, ¶1); and synthesizing the optimal hardware assertion checker set (p. 2121, §C; p. 2126, §IV, ¶1).
If Taatizadeh is found to be unclear regarding the cost prediction model, Mahmud discloses the same (Fig. 4; ¶29). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Taatizadeh and Mahmud, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of machine learning determination of circuit metrics. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Taatizadeh discloses determining overhead costs of hardware assertion checkers. Determining overhead costs using machine learning models is conventional; Mahmud provides one example. The teachings of Mahmud are directly applicable to Taatizadeh in the same way, so that Taatizadeh would similarly use machine learning to more conveniently determine overhead costs.
Regarding claim 2, Taatizadeh discloses that the cost prediction model is generated by: selecting hardware assertion checker subsets from a plurality of hardware assertion checkers and determining a plurality of overhead costs by, for each hardware assertion checker subset, determining an overhead cost associated with the hardware assertion checker subset by synthesizing and simulating the hardware assertion checker subset (p. 2121, Fig. 2, col. 1; p. 2121, §C), but does not appear to explicitly disclose training a regression model using the plurality of overhead costs. Mahmud discloses training a regression model using the plurality of overhead costs (¶¶25-26). Motivation to combine remains consistent with claim 1.
Regarding claim 3, Taatizadeh discloses that the plurality of overhead costs comprises one or more of power, area, thermal, temperature, accuracy, functional coverage, security, vulnerability coverage, or debuggability (p. 2120, §B; p. 2121, Fig. 2, col. 1; p. 2121, §C).
Regarding claim 4, Taatizadeh discloses that the optimal hardware assertion checker set is synthesized in reconfigurable hardware or a device with reconfigurability (p. 2119, col. 1, last par.). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to implement the teachings of Taatizadeh, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of increasing coverage with a limited number of assertions. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Taatizadeh discloses selecting a subset of assertions checkers to detect errors, and also discloses a reconfigurable block that increases assertion coverage through time multiplexing. Persons having ordinary skill in the art would recognize that these teachings are directly combinable to further improve coverage from a limited number of assertions through reconfiguration.
Regarding claim 7, Taatizadeh does not appear to explicitly disclose that the cost prediction model comprises a machine learning model; Mahmud discloses the same (¶29). Motivation to combine remains consistent with claim 1.
Regarding claim 8, Taatizadeh discloses that the hardware assertion checkers are associated with functional assertions (p. 2121, Fig. 2, col. 1; p. 2121, §C).
Regarding claim 9, Taatizadeh discloses that the hardware assertion checkers comprise one or more of functional checkers, security checkers, safety checkers, or reliability checkers (p. 2121, Fig. 2, col. 1).
Claims 10-13 and 16-18 are directed to systems comprising memory and processors configured to perform the methods of claims 1-4 and 7-9, and are rejected under the same reasoning. Taatizadeh further discloses systems comprising memory and processors configured to perform the claimed methods (p. 2126, §IV, ¶1).
Claims 19 and 20 are directed to storage media comprising instructions to perform the methods of claims 1 and 2, and are rejected under the same reasoning. Taatizadeh further discloses storage media comprising instructions to perform the claimed methods (p. 2126, §IV, ¶1).
Claim(s) 5, 6, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taatizadeh in view of Mahmud and Goswami (“Machine learning based fast and accurate High Level Synthesis design space exploration”).
Regarding claims 5 and 14, Taatizadeh does not appear to explicitly disclose that selecting the optimal hardware assertion checker set is further based at least in part on gradient descent, gradient descent with simulated annealing, or other minimization technique. Goswami discloses these limitations (p. 117, (b) and (c)). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Taatizadeh, Mahmud, and Goswami, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of optimizing assertions using conventional ML-based design optimization techniques. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Taatizadeh discloses selecting an optimum set of hardware assertion checkers that maximize coverage within design constraints. Gradient descent- and simulated annealing-based techniques are well-known for these types of optimization problems (e.g. selecting from a solution space to minimize/maximize some objective function); Goswami provides an example. The teachings of Goswami are directly applicable to Taatizadeh so that Taatizadeh would similarly use conventional machine learning techniques to optimize the selected set of assertions.
Regarding claims 6 and 15, Taatizadeh discloses that the optimal hardware assertion checker set comprises those hardware assertion checkers of the plurality of hardware assertion checkers satisfying the one or more design constraints while minimizing overhead cost (p. 2122, col. 1, ¶1; p. 2123, §III, ¶1). If Taatizadeh is found to be unclear regarding these limitations, Goswami also discloses the same (p. 121, Step 3). Motivation to combine remains consistent with claim 5.
Conclusion
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12 September 2026
/ARIC LIN/ Examiner, Art Unit 2851
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