DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traversing Group 1 Species I and Group 2, Species A directed to claims 1-3, 6, 11-13, 16 and 20 in the reply filed on 08/11/2026 is acknowledged. Claims 4-5, 7-10, 14-15 and 17-19 are directed towards non-elected species thereby withdrawn. No claims are cancelled. No claims were amended. No claims were added. As a result, claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-2, 6, 12, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rubin, Joshua M. (US 20200135646 A1) “Rubin et al.” in view of Lanzillo; Nicholas Anthony (US 20220406717 A1) “Lanzillo et al.”.
Regarding Independent Claim 1, Rubin et al. Figs. 1, 3-5, 10, 17 discloses a semiconductor structure (“a monolithic 3D semiconductor integrated circuit device 10” ¶ [0036]), comprising:
a backside interconnect (“a backside power distribution plane” ¶ [0069]) comprising a first metal layer and a second metal layer disposed on the first metal layer (“at least two stacked metallization layers wherein a first metallization layer comprises an array of parallel metal lines that extend in one direction (e.g., X-direction) and wherein a second metallization layer comprises an array of parallel metal lines that extend in another direction (e.g., Y-direction) orthogonal to the metal lines of the first metallization layer.” ¶ [0058]; “The BEOL layer comprises an interconnect structure, which comprises multiple levels of metal lines” ¶ [0041]),
the first metal layer comprising a first Vdd metal line and a first Vss metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]), and
the second metal layer comprising a second Vdd metal line and a second Vss metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]);
wherein the first Vss metal line is in contact with the second Vss metal line (“the GND lines of the first and second metallization layers are connected using vertical vias” ¶ [0058]); and
second Vss metal line is isolated from the first Vdd metal line (Fig. 1 shows GND line is isolated from Vdd line by dielectric)
However, Rubin et al. does not disclose, wherein the second Vss metal line is isolated from the first Vdd metal line by a non-conductive liner.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Lanzillo et al. Figs. 1, 4 and 11 discloses wherein the second Vss metal line is isolated from the first Vdd metal line by a non-conductive liner (“Dielectric material 30 will separate metal 20 forming the power and ground lines from the floating metal formed in later process steps.” ¶ [0073]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. by including a dielectric liner of Lanzillo et al. in order to provide increased capacitance to stabilize current flow to backside power lines is desirable. Furthermore, embodiments of the present invention recognize that decoupling capacitance in the backside metal layers of the power delivery network reduces power supply noise (Lanzillo et al., ¶ [0032]).
Regarding Claim 2, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 1. Rubin et al. further discloses, wherein the first Vdd metal line is in contact with the second Vdd metal line (“the VDD lines of the first and second metallization layers are connected using vertical vias” ¶ [0058]).
Regarding Claim 6, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 1. Rubin et al. Fig. 16A further discloses, wherein an interface between the first metal layer and the second metal layer is a uniform surface (“a CMP process to remove the overburden insulating material and planarize the surface” ¶ [0089]).
Regarding Independent Claim 12, Rubin et al. Figs. 1, 3-5, 10, 17 discloses a semiconductor structure (“a monolithic 3D semiconductor integrated circuit device 10” ¶ [0036]), comprising:
a backside interconnect (“a backside power distribution plane” ¶ [0069]) comprising a first metal layer and a second metal layer disposed on the first metal layer (“at least two stacked metallization layers wherein a first metallization layer comprises an array of parallel metal lines that extend in one direction (e.g., X-direction) and wherein a second metallization layer comprises an array of parallel metal lines that extend in another direction (e.g., Y-direction) orthogonal to the metal lines of the first metallization layer.” ¶ [0058]; “The BEOL layer comprises an interconnect structure, which comprises multiple levels of metal lines” ¶ [0041]),
the first metal layer comprising a first Vdd metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]), and
the second metal layer comprising a second Vdd metal line and a Vss metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]);
wherein the first Vdd metal line is in contact with the second Vdd metal line (“the VDD lines of the first and second metallization layers are connected using vertical vias” ¶ [0058]); and
Vss metal line is isolated from the Vdd metal line (Fig. 1 shows GND line is isolated from Vdd line by dielectric).
However, Rubin et al. does not disclose, wherein the first Vdd metal line is isolated from the Vss metal line by a non-conductive liner.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Lanzillo et al. Figs. 1, 4 and 11 discloses wherein the first Vdd metal line is isolated from the Vss metal line by a non-conductive liner (“Dielectric material 30 will separate metal 20 forming the power and ground lines from the floating metal formed in later process steps.” ¶ [0073]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. by including a dielectric liner of Lanzillo et al. in order to provide increased capacitance to stabilize current flow to backside power lines is desirable. Furthermore, embodiments of the present invention recognize that decoupling capacitance in the backside metal layers of the power delivery network reduces power supply noise (Lanzillo et al., ¶ [0032]).
Regarding Claim 16, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 12. Rubin et al. Fig. 16A further discloses, wherein an interface between the first metal layer and the second metal layer is a uniform surface (“a CMP process to remove the overburden insulating material and planarize the surface” ¶ [0089]).
Regarding Independent Claim 20, Rubin et al. Figs. 1, 3-5, 10, 17 discloses an integrated circuit (“a monolithic 3D semiconductor integrated circuit device 10” ¶ [0036]), comprising: one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a backside interconnect (“a backside power distribution plane” ¶ [0069]) comprising a first metal layer and a second metal layer disposed on the first metal layer (“at least two stacked metallization layers wherein a first metallization layer comprises an array of parallel metal lines that extend in one direction (e.g., X-direction) and wherein a second metallization layer comprises an array of parallel metal lines that extend in another direction (e.g., Y-direction) orthogonal to the metal lines of the first metallization layer.” ¶ [0058]; “The BEOL layer comprises an interconnect structure, which comprises multiple levels of metal lines” ¶ [0041]),
the first metal layer comprising a first Vdd metal line and a first Vss metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]), and
the second metal layer comprising a second Vdd metal line and a second Vss metal line (“the first and second metallization layers each comprise alternating VDD and GND metal lines” ¶ [0058]);
wherein the first Vss metal line is in contact with the second Vss metal line (“the GND lines of the first and second metallization layers are connected using vertical vias” ¶ [0058]); and
second Vss metal line is isolated from the first Vdd metal line (Fig. 1 shows GND line is isolated from Vdd line by dielectric)
However, Rubin et al. does not disclose, wherein the second Vss metal line is isolated from the first Vdd metal line by a non-conductive liner.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Lanzillo et al. Figs. 1, 4 and 11 discloses wherein the second Vss metal line is isolated from the first Vdd metal line by a non-conductive liner (“Dielectric material 30 will separate metal 20 forming the power and ground lines from the floating metal formed in later process steps.” ¶ [0073]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. by including a dielectric liner of Lanzillo et al. in order to provide increased capacitance to stabilize current flow to backside power lines is desirable. Furthermore, embodiments of the present invention recognize that decoupling capacitance in the backside metal layers of the power delivery network reduces power supply noise (Lanzillo et al., ¶ [0032]).
Claims 3, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Rubin, Joshua M. (US 20200135646 A1) “Rubin et al.” in view of Lanzillo; Nicholas Anthony (US 20220406717 A1) “Lanzillo et al.” further in view of Huang; Lin-Yu (US 20230369401 A1) “Huang et al.”.
Regarding Claim 3, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 1. However, Rubin et al. does not disclose, wherein the non-conductive liner comprises a dielectric material comprising SiN and HfO2.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Lanzillo et al. Figs. 1, 4 and 11 discloses, wherein the non-conductive liner comprises a dielectric material comprising HfO2 (“dielectric material 30 can be, but is not limited to a hafnium oxide material (e.g., HfO.sub.2)” ¶ [0072]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. by including a dielectric liner of Lanzillo et al. in order to provide increased capacitance to stabilize current flow to backside power lines is desirable. Furthermore, embodiments of the present invention recognize that decoupling capacitance in the backside metal layers of the power delivery network reduces power supply noise (Lanzillo et al., ¶ [0032]).
However, Lanzillo et al. does not disclose, wherein the non-conductive liner comprises a dielectric material comprising SiN and HfO2.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Huang et al. discloses, wherein the non-conductive liner (“a dielectric liner layer 304 on the backside of the structure 200.” ¶ [0037]) comprises a dielectric material comprising SiN and HfO2 (“the dielectric liner layer 304 may include …. HfO.sub.2, Si.sub.3N.sub.4, or other suitable material(s).” ¶ [0037]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. as modified by Lanzillo et al. by including a dielectric liner of Huang et al. because the selection of a high k dielectric material for dielectric material can provide increase capacitance in the completed semiconductor chip (Lanzillo et al., ¶ [0073]).
Regarding Claim 13, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 12. However, Rubin et al. does not disclose, wherein the non-conductive liner comprises a dielectric material comprising SiN and HfO2.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Lanzillo et al. Figs. 1, 4 and 11 discloses, wherein the non-conductive liner comprises a dielectric material comprising HfO2 (“dielectric material 30 can be, but is not limited to a hafnium oxide material (e.g., HfO.sub.2)” ¶ [0072]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. by including a dielectric liner of Lanzillo et al. in order to provide increased capacitance to stabilize current flow to backside power lines is desirable. Furthermore, embodiments of the present invention recognize that decoupling capacitance in the backside metal layers of the power delivery network reduces power supply noise (Lanzillo et al., ¶ [0032]).
However, Lanzillo et al. does not disclose, wherein the non-conductive liner comprises a dielectric material comprising SiN and HfO2.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers Huang et al. discloses, wherein the non-conductive liner (“a dielectric liner layer 304 on the backside of the structure 200.” ¶ [0037]) comprises a dielectric material comprising SiN and HfO2 (“the dielectric liner layer 304 may include …. HfO.sub.2, Si.sub.3N.sub.4, or other suitable material(s).” ¶ [0037]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd and Vss lines of Rubin et al. as modified by Lanzillo et al. by including a dielectric liner of Huang et al. because the selection of a high k dielectric material for dielectric material can provide increase capacitance in the completed semiconductor chip (Lanzillo et al., ¶ [0073]).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rubin, Joshua M. (US 20200135646 A1) “Rubin et al.” in view of Lanzillo; Nicholas Anthony (US 20220406717 A1) “Lanzillo et al.” further in view of ZHU; John Jianhong (US 20210217699 A1) “ZHU et al.”.
Regarding Claim 11, Rubin et al. as modified by Lanzillo et al. discloses the limitations of claim 2. Rubin et al. further discloses, wherein a TaN or a TiN liner layer is disposed between the metal lines (“The MOL contacts C1, C2, and C3 (and horizontal interconnect wiring) may comprise metallic fill material including, but not limited to, tungsten, cobalt, ruthenium, copper, or combinations thereof, as well as thin liner layers (e.g., titanium nitride (TiN) and/or tantalum nitride (TaN) barrier layer and/or seed layer) which are formed prior to depositing the metallic fill material.” ¶ [0038]).
However, Rubin et al. does not disclose, wherein a TaN or a TiN liner layer is disposed between the first Vdd metal line and the second Vdd metal line.
In the similar field of endeavor of semiconductor structure with one or more backside metal layers ZHU et al. discloses, wherein a TaN or a TiN liner layer (“the barrier layer 240 may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or titanium-tungsten (TiW).” ¶ [0045]) is disposed between the first Vdd metal line and the second Vdd metal line (“the power rail 128 includes a first conductive layer 238, a barrier layer 240, and a second conductive layer 242. The barrier layer 240 is disposed between the first conductive layer 238 and second conductive layer 242.” ¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the Vdd lines of Rubin et al. as modified by Lanzillo et al. by including a dielectric liner of ZHU et al. in order to serve as a seed layer when forming or depositing the second conductive layer (ZHU et al., ¶ [0045]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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